Renesas 89HPES24T3G2ZBAL, User Manual

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Notes
PES24T3G2 User Manual 5 - 1 February 22, 2012
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Chapter 5
SMBus Interfaces
Introduction
The PES24T3G2 contains two SMBus interfaces. The slave SMBus interface provides full access to all
software visible registers in the PES24T3G2, allowing every register in the device to be read or written by
an external SMBus master. The slave SMBus may also be used to initialize the serial EEPROM used for
initialization. The Master SMBus interface provides connection for an optional external serial EEPROM
used for initialization and optional external I/O expanders.
Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an
SMBus data pin, and 4 SMBus address pins.
Note: MSMBADDR and SSMBADDR address pins are not available in the 19mm package. The
MSMBADDR address is hardwired to 0x50, and the SSMBADDR address is hardwired to 0x77.
As shown in Figure 5.1, the master and slave SMBuses may be used in a unified or split configuration.
Figure 5.1 SMBus Interface Configuration Examples
In the unified configuration, shown in Figure 5.1(a), the master and slave SMBuses are tied together and
the PES24T3G2 acts both as an SMBus master as well as an SMBus slave on this bus. This requires that
the external SMBus master or processor that has access to the PES24T3G2 registers support SMBus arbi-
Processor
PES24T3G2
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
SMBus
Master
Other
SMBus
Devices
Serial
EEPROM
Processor
PES24T3G2
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
SMBus
Master
Other
SMBus
Devices
Serial
EEPROM
...
...
(a) Unified Configuration
(b) Split Configuration
Hot-Plug
I/O
Expander
Hot-Plug
I/O
Expander