Renesas 89HPES24T3G2ZBAL, User Manual

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IDT PES24T3G2 Device Overview
PES24T3G2 User Manual 1 - 4 February 22, 2012
Logic Diagram — PES24T3G2
Figure 1.2 PES24T3G2 Logic Diagram
Note: The following pins are not available in the 19mm package: REFCLKM, MSMBADDR, SSMBADDR, MSMBSMODE, RSTHALT,
GPIO[6:3].
Vendor ID
All vendor IDs in the device are hardwired to 0x111D which corresponds to Integrated Device Technology, Inc.
Reference
Clocks
PEREFCLKP
PEREFCLKN
JTAG_TCK
GPIO[10:0]
11
General Purpose
I/O*
V
DD
CORE
V
DD
I/O
V
DD
PEA
Power/Ground
MSMBADDR[4:1]
MSMBCLK
MSMBDAT
4
SSMBADDR[5,3:1]
SSMBCLK
SSMBDAT
4
Master
SMBus Interface
Slave
SMBus Interface
CCLKUS
RSTHALT
System
Pins
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
JTAG Pins
V
SS
SWMODE[2:0]
3
CCLKDS
PERSTN
REFCLKM
MSMBSMODE
PE0RP[0]
PE0RN[0]
PE0RP[7]
PE0RN[7]
PCI Express
Switch
SerDes Input
PE0TP[0]
PE0TN[0]
PE0TP[7]
PE0TN[7]
PCI Express
Switch
SerDes Output
...
Port 0
Port 0
...
PE2RP[0]
PE2RN[0]
PE2RP[7]
PE2RN[7]
PCI Express
Switch
SerDes Input
PE2TP[0]
PE2TN[0]
PE2TP[7]
PE2TN[7]
PCI Express
Switch
SerDes Output
...
Port 2
Port 2
...
PE4RP[0]
PE4RN[0]
PE4RP[7]
PE4RN[7]
PCI Express
Switch
SerDes Input
PE4TP[0]
PE4TN[0]
PE4TP[7]
PE4TN[7]
PCI Express
Switch
SerDes Output
...
Port 4
Port 4
...
PES24T3G2
REFRES0
SerDes
Reference
Resistors
REFRES2
REFRES4
REFRES5
V
DD
PEHA
Reference Clock
Frequency Selection
REFRES1
REFRES3
V
DD
PETA