Renesas 89HPES24T3G2ZBAL, User Manual

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IDT JTAG Boundary Scan
PES24T3G2 User Manual 9 - 8 February 22, 2012
Notes
VALIDATE
The VALIDATE instruction is automatically loaded into the instruction register whenever the TAP
controller passes through the CAPTURE-IR state. The lower two bits ‘01’ are mandated by the IEEE Std.
1149.1 specification.
RESERVED
Reserved instructions implement various test modes used in the device manufacturing process. The
user should not enable these instructions.
Usage Considerations
As previously stated, there are internal pull-ups on JTAG_TRST_N, JTAG_TMS, and JTAG_TDI.
However, JTAG_TCK also needs to be driven to a known value. It is best to either drive a zero on the
JTAG_TCK pin when it is not being used or to use an external pull-down resistor. In order to guarantee that
the JTAG does not interfere with normal system operation, the TAP controller should be forced into the Test-
Logic-Reset controller state by continuously holding JTAG_TRST_N low and/or JTAG_TMS high when the
chip is in normal operation. If JTAG will not be used, externally pull-down JTAG_TRST_N low to disable it.