Renesas 89HPES24T3G2ZBAL, User Manual

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IDT PES24T3G2 Device Overview
PES24T3G2 User Manual 1 - 10 February 22, 2012
Notes
Pin Characteristics
Note: Some input pads of the PES24T3G2 do not contain internal pull-ups or pull-downs.
Unused inputs should be tied off to appropriate levels. This is especially critical for unused control
signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating
can cause a slight increase in power consumption.
Function Pin Name Type Buffer
I/O
Type
Internal
Resistor
1
Notes
PCI Express
Interface PE0RN[7:0] I PCIe
differential
2
Serial Link
PE0RP[7:0] I
PE0TN[7:0] O
PE0TP[7:0] O
PE2RN[7:0] I
PE2RP[7:0] I
PE2TN[7:0] O
PE2TP[7:0] O
PE4RN[7:0] I
PE4RP[7:0] I
PE4TN[7:0] O
PE4TP[7:0] O
PEREFCLKN I HCSL Diff. Clock
Input
Refer to Table 9
in the
PES24T3G2
Data Sheet
PEREFCLKP I
REFCLKM
3
I LVTTL Input pull-down
SMBus MSMBADDR[4:1]
4
I LVTTL Input pull-down
MSMBCLK I/O STI
5
pull-up on board
MSMBDAT I/O STI pull-up on board
SSMBADDR[5,3:1]
4
I Input pull-up
SSMBCLK I/O STI pull-up on board
SSMBDAT I/O STI pull-up on board
General Pur-
pose I/O GPIO[10:0]
6
I/O LVTTL STI,
High Drive
pull-up
System Pins CCLKDS I LVTTL Input pull-up
CCLKUS I Input pull-up
MSMBSMODE
7
I Input pull-down
PERSTN I STI
RSTHALT
7
I Input pull-down
SWMODE[2:0] I Input pull-down
Table 1.9 Pin Characteristics (Part 1 of 2)