Renesas 89HPES24T3G2ZBAL, User Manual

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IDT Configuration Registers
PES24T3G2 User Manual 8 - 42 February 22, 2012
Notes
5 SDOENERR RW 0x0
Sticky
Surprise Down Error Mask. When this bit is set, the corre-
sponding bit in the AERUES register is masked. When a bit is
masked in the AERUES register, the corresponding event is not
logged in the advanced capability structure, the First Error
Pointer field (FEPTR) in the AERCTL register is not updated, and
an error is not reported to the root complex.
This bit does not affect the state of the corresponding bit in the
AERUES register.
11:6 Reserved RO 0x0 Reserved field.
12 POISONED RW 0x0
Sticky
Poisoned TLP Mask. When this bit is set, the corresponding bit
in the AERUES register is masked. When a bit is masked in the
AERUES register, the corresponding event is not logged in the
advanced capability structure, the First Error Pointer field
(FEPTR) in the AERCTL register is not updated, and an error is
not reported to the root complex.
This bit does not affect the state of the corresponding bit in the
AERUES register.
13 FCPERR RW 0x0
Sticky
Flow Control Protocol Error Mask. When this bit is set, the cor-
responding bit in the AERUES register is masked. When a bit is
masked in the AERUES register, the corresponding event is not
logged in the advanced capability structure, the First Error
Pointer field (FEPTR) in the AERCTL register is not updated, and
an error is not reported to the root complex.
This bit does not affect the state of the corresponding bit in the
AERUES register.
14 COMPTO RO 0x0 Completion Time-out Mask. A switch port does not initiate non-
posted requests on its own behalf. Therefore, this field is hard-
wired to zero.
15 CABORT RO 0x0 Completer Abort Mask. The PES24T3G2 never responds to a
non-posted request with a completer abort.
16 UECOMP RW 0x0
Sticky
Unexpected Completion Mask. When this bit is set, the corre-
sponding bit in the AERUES register is masked. When a bit is
masked in the AERUES register, the corresponding event is not
logged in the advanced capability structure, the First Error
Pointer field (FEPTR) in the AERCTL register is not updated, and
an error is not reported to the root complex.
This bit does not affect the state of the corresponding bit in the
AERUES register.
17 RCVOVR RW 0x0
Sticky
Receiver Overflow Mask. When this bit is set, the corresponding
bit in the AERUES register is masked. When a bit is masked in
the AERUES register, the corresponding event is not logged in
the advanced capability structure, the First Error Pointer field
(FEPTR) in the AERCTL register is not updated, and an error is
not reported to the root complex.
This bit does not affect the state of the corresponding bit in the
AERUES register.
Bit
Field
Field
Name
Type
Default
Value
Description