Renesas 89HPES24T3G2ZBAL, User Manual

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IDT SMBus Interfaces
PES24T3G2 User Manual 5 - 17 February 22, 2012
Notes
Sample Slave SMBus Operation
This section illustrates sample Slave SMBus operations. Shaded items are driven by the PES24T3G2’s
slave SMBus interface and non-shaded items are driven by an SMBus host.
Figure 5.8 CSR Register Read Using SMBus Block Write/Read Transactions with PEC Disabled
Figure 5.9 Serial EEPROM Read Using SMBus Block Write/Read Transactions with PEC Disabled
5 OTHERERR RC Other Error. This bit is set if a misplaced START or STOP condition is
detected by the master SMBus interface when accessing the serial
EEPROM. This bit has the same function as the OTHERERR bit in the
SMBUSSTS register.
7:6 Reserved 0 Reserved. Must be zero
1.
See Table Table 2 in the About This Manual chapter for a definition of these abbreviations.
Bit
Field
Name Type
1
Description
Table 5.14 Serial EEPROM Read or Write CMD Field Description
DATAUU N DATAUM A
BYTCNT=7 A ADDRL CMD (status)
S
PES24T3G2 Slave
SMBus Address
Wr A A BYTCNT=3 A CMD=read A ADDRL A ADDRU A P
CCODE
START,END
S
PES24T3G2 Slave
SMBus Address
Wr A A
CCODE
START,END
S
PES24T3G2 Slave
SMBus Address
Rd
DATALM DATALL
A A A
A N P ADDRU A
S
PES24T3G2 Slave
SMBus Address
Wr A N
CCODE
START,END
P
(PES24T3G2 not ready with data)
S
PES24T3G2 Slave
SMBus Address
Wr A A BYTCNT=4 A CMD=read A EEADDR A ADDRL A
P
CCODE
START,END
S
PES24T3G2 Slave
SMBus Address
Wr A A
CCODE
START,END
S
PES24T3G2 Slave
SMBus Address
Rd
ADDRU A
BYTCNT=5 A EEADDR CMD (status) A A A
N DATA ADDRU A P ADDRL A
S
PES24T3G2 Slave
SMBus Address
Wr A N
CCODE
START,END
P
(PES24T3G2 not ready with data)