Renesas 89HPES24T3G2ZBAL, User Manual

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IDT JTAG Boundary Scan
PES24T3G2 User Manual 9 - 6 February 22, 2012
Notes
Instruction Register (IR)
The Instruction register allows an instruction to be shifted serially into the device at the rising edge of
JTAG_TCK. The instruction is then used to select the test to be performed or the test register to be
accessed, or both. The instruction shifted into the register is latched at the completion of the shifting
process, when the TAP controller is at the Update-IR state.
The Instruction register contains six shift-register-based cells that can hold instruction data. This register
is decoded to perform the following functions:
– To select test data registers that may operate while the instruction is current. The other test data
registers should not interfere with chip operation and selected data registers.
– To define the serial test data register path used to shift data between JTAG_TDI and JTAG_TDO
during data register scanning.
The Instruction register is comprised of 6 bits to decode instructions, as shown in Table 9.3.
EXTEST
The external test (EXTEST) instruction is used to control the boundary scan register, once it has been
initialized using the SAMPLE/PRELOAD instruction. Using EXTEST, the user can then sample inputs from
or load values onto the external pins of the PES24T3G2. Once this instruction is selected, the user then
uses the SHIFT-DR TAP controller state to shift values into the boundary scan chain. When the TAP
controller passes through the UPDATE-DR state, these values will be latched onto the output pins or into
the output enables.
Instruction Definition Opcode
EXTEST Mandatory instruction allowing the testing of board level interconnec-
tions. Data is typically loaded onto the latched parallel outputs of the
boundary scan shift register using the SAMPLE/PRELOAD instruction
prior to use of the EXTEST instruction. EXTEST will then hold these
values on the outputs while being executed. Also see the CLAMP
instruction for similar capability. 000000
SAMPLE/
PRELOAD
Mandatory instruction that allows data values to be loaded onto the
latched parallel output of the boundary scan shift register prior to
selection of the other boundary scan test instruction. The Sample
instruction allows a snapshot of data flowing from the system pins to
the on-chip logic or vice versa. 000001
IDCODE Provided to select Device Identification to read out manufacturer’s
identity, part, and version number. 000010
HIGHZ Tri-states all output and bidirectional boundary scan cells. 000011
RESERVED 000100 —
101100
VALIDATE Automatically loaded into the instruction register whenever the TAP
controller passes through the CAPTURE-IR state. The lower two bits
‘01’ are mandated by the IEEE Std. 1149.1 specification. 101101
RESERVED 101110 —
111101
CLAMP Provides JTAG users with the option to bypass the part’s JTAG con-
troller while keeping the part outputs controlled similar to EXTEST. 111110
BYPASS The BYPASS instruction is used to truncate the boundary scan regis-
ter as a single bit in length. 111111
Table 9.3 Instructions Supported by PES24T3G2’s JTAG Boundary Scan