Renesas 89HPES24T3G2ZBAL, User Manual

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IDT Clocking, Reset and Initialization
PES24T3G2 User Manual 2 - 4 February 22, 2012
Notes
PES24T3G2 responds to a Configuration Request with Configuration-Request-Retry-Status Completion.
Under normal circumstances, 200 ms is more than adequate to initialize registers in the device even with a
Master SMBus operating frequency of 100 KHz.
Serial EEPROM initialization may cause writes to register fields that initiate side effects, such as link
retraining. These side effects are initiated at the point where the write occurs. Therefore, serial EEPROM
initialization should be structured in a manner so as to ensure proper configuration prior to initiation of these
side effects.
A warm reset initiated by a configuration request writing a one to the Fundamental Reset (FRST) bit in
the Switch Control (SWCTL) register always results in the PES24T3G2 returning a Successful Completion
to the requester
before the warm reset process begins. The PES24T3G2 provides a reset output signal for
each downstream port implemented as a GPIO alternate function. When a Fundamental Reset occurs, all
of the GPIO pins default to GPIO inputs. Therefore, the downstream port resets are tri-stated. A system
designer should use a pull-down on these signals if they are used as reset outputs.
The operation of a Fundamental Reset with serial EEPROM initialization (i.e., SWMODE[2:0] = 0x1) is
illustrated in Figure 2.1.
Figure 2.1 Fundamental Reset with Serial EEPROM initialization
The operation of a Fundamental Reset using RSTHALT is illustrated in Figure 2.2.
REFCLK*
Vdd
PERSTN
SerDes
Master SMBus
Slave SMBus
Tpvperl (100ms)
CDR Reset & Lock
Ready for Normal Operation
Ready for Normal Operation
Ready Idle
Serial EEPROM Initialization
~70
μ
s
20 ms max.
Stacks held in Quasi-Reset Mode
Link Training
50 µ s max
PLL Lock
Tperst-clk
(100µ s)
Notes:
1) Reference Clock (REFCLK) not shown to scale.
2) The PES24T3G2 requires a minimum time for Tperst-clk of 1µs. The PES24T3G2 requires a minimum time for Tpvperl of 1ms.
3) In a system, the values of Tpvperl and Tperst-clk depend on the mechanical form factor in which the PES24T3G2 is used. For example,
the PCIe Card Electromechanical Specification, Revision 2.0, specifies minimum values of Tperst-clk=100µs and Tpvperl=100ms.