Renesas 89HPES24T3G2ZBAL, User Manual

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IDT SMBus Interfaces
PES24T3G2 User Manual 5 - 13 February 22, 2012
Notes
Initialization
Slave SMBus initialization occurs during a fundamental reset (see section Fundamental Reset on page
2-2). During the fundamental reset initialization sequence, the slave SMBus address is initialized. The
address is specified by the SSMBADDR[5,3:1] signals as shown in Table 5.9.
Note: SSMBADDR address pins are not available in the 19mm package. The SSMBADDR
address is hardwired to 0x77.
SMBus Transactions
The slave SMBus interface responds to the following SMBus transactions initiated by an SMBus master
(see the SMBus 2.0 specification for a detailed description of these transactions):
– Byte and Word Write/Read
– Block Write/Read
Initiation of any SMBus transaction other than those listed above to the slave SMBus interface produces
undefined results. Associated with each of the above transactions is a command code. The command code
format for operations supported by the slave SMBus interface is shown in Figure 5.5 and described in Table
5.10.
Figure 5.5 Slave SMBus Command Code Format
Address Bit Address Bit Value
1 SSMBADDR[1]
2 SSMBADDR[2]
3 SSMBADDR[3]
4 0
5 SSMBADDR[5]
6 1
7 1
Table 5.9 Slave SMBus Address When a Static Address is Selected
Bit
Field
Name Description
0 END End of transaction indicator. Setting both START and END signifies a
single transaction sequence
0 - Current transaction is not the last read or write sequence.
1 - Current transaction is the last read or write sequence.
1 START Start of transaction indicator. Setting both START and END signifies a
single transaction sequence
0 - Current transaction is not the first of a read or write sequence.
1 - Current transaction is the first of a read or write sequence.
Table 5.10 Slave SMBus Command Code Fields (Part 1 of 2)
Bit
6
Bit
7
Bit
0
Bit
1
Bit
2
Bit
3
Bit
4
Bit
5
END START FUNCTION SIZE PEC