Renesas 89HPES24T3G2ZBAL, User Manual

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IDT Clocking, Reset and Initialization
PES24T3G2 User Manual 2 - 8 February 22, 2012
Notes
Power Good Controlled Reset Output
As in the Power Enable Controlled Reset mode, in this mode a downstream port reset output state is
controlled as a side effect of slot power being turned on or off. However, the timing in this mode depends on
the power good state of the slot’s power supply. The operation of this mode is illustrated in Figure 2.4.
Figure 2.4 Power Good Controlled Reset Output Mode Operation
The operation of this mode is similar to that of the Power Enable Controlled Reset mode except that
when power is enabled, the negation of the corresponding port reset output occurs as a result of and after
assertion of the slot’s Power Good (PxPWRGDN) signal is observed. The time between the assertion of the
PxPWRGDN signal and the negation of the PxRSTN signal is controlled by the value in the Slot Power to
Reset Negation (PWR2RST) field in the HPCFGCTL register.
When slot power is disabled by writing a one to the PCC bit, the corresponding downstream port reset
output is asserted and then slot power is disabled. The time between the assertion of the PxRSTN signal
and the negation of the PxPEP signal is controlled by the value in the Reset Negation to Slot Power
(RST2PWR) field in the HPCFGCTL register.
If at any point while a downstream port is not being reset (i.e., PxRSTN is negated) a power fault is
detected (i.e., PxPWRGDN is negated), then the corresponding port reset output is immediately asserted.
Since the PxPWRGDN signal is an I/O expander input, it may not be possible to meet a profile’s power level
invalid to reset asserted timing specification (i.e., PxPWRGDN to PxRSTN). Systems that require a shorter
time interval may implement this functionality external to the PES24T3G2.
PxPEP
PxPWRGDN
T
PWR2RST
PxRSTN
T
RST2PWR