Renesas 89HPES24T3G2ZBAL, User Manual

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IDT Configuration Registers
PES24T3G2 User Manual 8 - 20 February 22, 2012
Notes
PCI Express Capability Structure
PCIECAP - PCI Express Capability (0x040)
4 VGA16EN RW 0x0 VGA 16-bit Enable. This bit only has an effect when the VGAEN
bit is set in this register.
This read/write bit enables system configuration software to
select between 10-bit and 16-bit I/O space decoding for VGA
transactions.
0 - (bit10) Perform 10-bit decoding. I/O space aliasing occurs in
this mode.
1 - (bit16) Perform 16-bit decoding. No I/O space aliasing occurs
in this mode.
5 Reserved RO 0x0 Reserved field.
6 SRESET RW 0x0 Secondary Bus Reset. Setting this bit triggers a secondary bus
reset.
In the upstream port, setting this bit initiates a Upstream Second-
ary Bus Reset.
In a downstream port, setting this bit initiates a Downstream Sec-
ondary Bus Reset.
Port Configuration Registers must not be changed except as
required to update port status.
15:7 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description
7:0 CAPID RO 0x10 Capability ID. The value of 0x10 identifies this capability as a
PCI Express capability structure.
15:8 NXTPTR RWL 0xC0 Next Pointer. This field contains a pointer to the next capability
structure.
19:16 VER RWL 0x2 PCI Express Capability Version. This field indicates the PCI-
SIG defined PCI Express capability structure version number.
The PES24T3G2 is compliant with the Express Capabilities Reg-
ister Expansion ECN.
23:20 TYPE RO Upstream:
0x5
Downstream:
0x6
Port Type. This field identifies the type of switch port (upstream
or downstream).
24 SLOT RWL 0x0 Slot Implemented. This bit is set when the PCI Express link
associated with this Port is connected to a slot. This field does
not apply to an upstream port and should be set to zero.
29:25 IMN RO 0x0 Interrupt Message Number. The function is allocated only one
MSI. Therefore, this field is set to zero.
31:30 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description