Renesas 89HPES24T3G2ZBAL, User Manual

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IDT Configuration Registers
PES24T3G2 User Manual 8 - 33 February 22, 2012
Notes
PCIEDCTL2 - PCI Express Device Control 2 (0x068)
PCIEDSTS2 - PCI Express Device Status 2 (0x06A)
PCIELCAP2 - PCI Express Link Capabilities 2 (0x06C)
PCIELCTL2 - PCI Express Link Control 2 (0x070)
Bit
Field
Field
Name
Type
Default
Value
Description
4:0 Reserved RO 0x0 Reserved field.
5 ARIFEN RO 0x0 ARI Forwarding Enable. When set, the downstream port dis-
ables its traditional Device Number field being zero enforcement
when turning a Type 1 configuration request into a Type 0 config-
uration request, permitting access to the Extended Functions in
an ARI device immediately below the port.
When the ARIFS bit in the PCIEDCAP2 register is cleared, this
bit is read-only zero.
This bit is always read-only zero in the upstream port.
15:6 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description
15:0 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description
31:0 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description
3:0 TLS RW 0x2
Sticky
Target Link Speed. For downstream ports, this field sets an
upper limit on the link operational speed by restricting the values
advertised by the upstream component in its training sequences.
For both upstream and downstream ports, this field is used to set
the target compliance mode speed when software is using the
ECOMP bit in this register to force a link into compliance mode.
The PES24T3G2 supports 2.5 Gbps and 5.0 Gbps operation.
Setting this field to an unsupported value produces undefined
results.
0x1 - (gen1) 2.5 Gbps
0x2 - (gen2) 5.0 Gbps
others - reserved
4 ECOMP RW 0x0
Sticky
Enter Compliance. Software is permitted to force a link into
compliance mode at the speed indicated by the TLS field by set-
ting this bit in both components on a link and then initiating a hot
reset on the link.