Renesas 89HPES24T3G2ZBAL, User Manual

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IDT Configuration Registers
PES24T3G2 User Manual 8 - 37 February 22, 2012
Notes
PMCSR - PCI Power Management Control and Status (0x0C4)
Message Signaled Interrupt Capability Structure
MSICAP - Message Signaled Interrupt Capability and Control (0x0D0)
Bit
Field
Field
Name
Type
Default
Value
Description
1:0 PSTATE RW 0x0 Power State. This field is used to determine the current power
state and to set a new power state.
0x0 - (d0) D0 state
0x1 -(d1) D1 state (not supported by the PES24T3G2 and
reserved)
0x2- (d2) D2 state (not supported by the PES24T3G2 and
reserved)
0x3 -(d3) D3
hot
state
2 Reserved RO 0x0
3 NOSOFTRST RWL 0x1 No Soft Reset. This bit indicates if the configuration context is
preserved by the bridge when the device transitions from a D3hot
to D0 power management state.
0x0 - (reset) State reset
0x1 - (preserved) State preserved
7:4 Reserved RO 0x0
8 PMEE RW 0x0
Sticky
PME Enable. When this bit is set, PME message generation is
enabled for the port.
If a hot plug wake-up event is desired when exiting the D3
cold
state, then this bit should be set during serial EEPROM initializa-
tion.
A hot reset does not result in modification of this field.
12:9 DSEL RO 0x0 Data Select. The optional data register is not implemented.
14:13 DSCALE RO 0x0 Data Scale. The optional data register is not implemented.
15 PMES RW1C 0x0
Sticky
PME Status. This bit is set if a PME is generated by the port
even if the PMEE bit is cleared. This bit is not set when the bridge
is propagating a PME message but the port is not itself generat-
ing a PME.
Since the upstream port never generates a PME, this bit will
never be set in that port.
21:16 Reserved RO 0x0 Reserved field.
22 B2B3 RO 0x0 B2/B3 Support. Does not apply to PCI Express.
23 BPCCE RO 0x0 Bus Power/Clock Control Enable. Does not apply to PCI
Express.
31:24 DATA RO 0x0 Data. This optional field is not implemented.
Bit
Field
Field
Name
Type
Default
Value
Description
7:0 CAPID RO 0x5 Capability ID. The value of 0x5 identifies this capability as a MSI
capability structure.