Renesas 89HPES24T3G2ZBAL, User Manual

Page: 144 / 165

IDT Configuration Registers
PES24T3G2 User Manual 8 - 62 February 22, 2012
Notes
GPIOCFG - General Purpose I/O Configuration (0x41C)
GPIOD - General Purpose I/O Data (0x420)
SMBUSSTS - SMBus Status (0x424)
Bit
Field
Field
Name
Type
Default
Value
Description
15:0 GPIOCFG RW 0x0
Sticky
GPIO Configuration. Each bit in this field controls the corre-
sponding GPIO pin. When a bit is configured as a general pur-
pose I/O pin and the corresponding bit in this field is set, then the
pin is configured as a GPIO output. When a bit is configured as a
general purpose I/O pin and the corresponding bit in this field is
zero, then the pin is configured as an input. When the pin is con-
figured as an alternate function, the behavior of the pin is defined
by the alternate function.
31:16 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description
15:0 GPIOD RW HWINIT
Sticky
GPIO Data. Each bit in this field controls the corresponding GPIO
pin. Reading this field returns the current value of each GPIO pin
regardless of GPIO pin mode (i.e., alternate function or GPIO
pin). Writing a value to this field causes the corresponding pins
which are configured as GPIO outputs to change state to the
value written.
31:16 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description
0 Reserved RO 0x0 Reserved field.
7:1 SSMBADDR RO HWINIT Slave SMBus Address. This field contains the SMBus address
assigned to the slave SMBus interface.
8 Reserved RO 0x0 Reserved field.
15:9 MSMBADDR RO HWINIT Master SMBus Address. This field contains the SMBus address
assigned to the master SMBus interface.
23:16 Reserved RO 0x0 Reserved field.
24 EEPROM-
DONE
RO 0x0 Serial EEPROM Initialization Done. When the switch is config-
ured to operate in a mode in which serial EEPROM initialization
occurs during a Fundamental Reset, this bit is set when serial
EEPROM initialization completes or when an error is detected.
25 NAERR RW1C 0x0 No Acknowledge Error. This bit is set if an unexpected NACK is
observed during a master SMBus transaction. The setting of this
bit may indicate the following: that the addressed device does not
exist on the SMBus (i.e., addressing error); data is unavailable or
the device is busy; an invalid command was detected by the
slave; or invalid data was detected by the slave.