Renesas 89HPES24T3G2ZBAL, User Manual

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Notes
PES24T3G2 User Manual vii February 22, 2012
List of Figures
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Figure 1.1 PES24T3G2 Architectural Block Diagram ..........................................................................1-3
Figure 1.2 PES24T3G2 Logic Diagram ...............................................................................................1-4
Figure 1.3 PES24T3G2 Port Configuration .......................................................................................1-11
Figure 2.1 Fundamental Reset with Serial EEPROM initialization ......................................................2-4
Figure 2.2 Fundamental Reset using RSTHALT to keep device in Quasi-Reset state .......................2-5
Figure 2.3 Power Enable Controlled Reset Output Mode Operation ..................................................2-7
Figure 2.4 Power Good Controlled Reset Output Mode Operation .....................................................2-8
Figure 3.1 Merged Port Lane Reversal ...............................................................................................3-2
Figure 3.2 PES24T3G2 ASPM Link Sate Transitions .........................................................................3-9
Figure 5.1 SMBus Interface Configuration Examples .........................................................................5-1
Figure 5.2 Single Double Word Initialization Sequence Format ..........................................................5-3
Figure 5.3 Sequential Double Word Initialization Sequence Format ...................................................5-4
Figure 5.4 Configuration Done Sequence Format ..............................................................................5-4
Figure 5.5 Slave SMBus Command Code Format ............................................................................5-13
Figure 5.6 CSR Register Read or Write CMD Field Format ..............................................................5-15
Figure 5.7 Serial EEPROM Read or Write CMD Field Format ..........................................................5-16
Figure 5.8 CSR Register Read Using SMBus Block Write/Read Transactions with PEC Disabled ..5-17
Figure 5.9 Serial EEPROM Read Using SMBus Block Write/Read Transactions with PEC
Disabled ...........................................................................................................................5-17
Figure 5.10 CSR Register Write Using SMBus Block Write Transactions with PEC Disabled ...........5-18
Figure 5.11 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Disabled ........5-18
Figure 5.12 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Enabled ........5-18
Figure 5.13 CSR Register Read Using SMBus Read and Write Transactions with PEC Disabled ....5-19
Figure 6.1 PES24T3G2 Power Management State Transition Diagram .............................................6-1
Figure 7.1 Hot-Plug on Switch Downstream Slots Application ............................................................7-1
Figure 7.2 Hot-Plug with Switch on Add-In Card Application ..............................................................7-2
Figure 7.3 Hot-Plug with Carrier Card Application ..............................................................................7-2
Figure 7.4 PES24T3G2 Hot-Plug Event Signalling .............................................................................7-6
Figure 8.1 Port Configuration Space Organization .............................................................................8-2
Figure 9.1 Diagram of the JTAG Logic ................................................................................................9-1
Figure 9.2 State Diagram of PES24T3G2’s TAP Controller ................................................................9-2
Figure 9.3 Diagram of Observe-only Input Cell ...................................................................................9-4
Figure 9.4 Diagram of Output Cell ......................................................................................................9-5
Figure 9.5 Diagram of Bidirectional Cell ..............................................................................................9-5
Figure 9.6 Device ID Register Format .................................................................................................9-7