Renesas 89HPES24T3G2ZBAL, User Manual

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IDT Configuration Registers
PES24T3G2 User Manual 8 - 56 February 22, 2012
Notes
PWRBD - Power Budgeting Data (0x288)
PWRBPBC - Power Budgeting Power Budget Capability (0x28C)
PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C)
Switch Control and Status Registers
SWSTS - Switch Status (0x400)
Bit
Field
Field
Name
Type
Default
Value
Description
31:0 DATA RO 0x0 Data. If the Data Value Select (DVSEL) field in the Power Bud-
geting Data Select register contains a value of zero through 7,
then this field returns the contents of the corresponding Power
Budgeting Data Value (PWRBDVx) register. Otherwise, this field
contains a value of zero.
Bit
Field
Field
Name
Type
Default
Value
Description
0 SA RWL 0x0 System Allocated. When this bit is set, it indicates that the
power budget for the device is included within the system power
budget and that reported power data for this device should be
ignored.
If the power budgeting capability is used, then this field should be
initialized with data from a serial EEPROM.
31:1 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description
31:0 DV RW Undefined
Sticky
Data Value. This 32-bit field is used to hold power budget data in
the format described in Section 7.15.3 in the PCIe 2.0 Base
Specification.
This field may be read and written when the Power Budgeting
Data Value Unlock (PWRBDVUL) bit is set in the Switch Control
(SWCTL) register. When the PWRBDVUL bit is cleared, this reg-
ister is read-only and writes are ignored.
If the power budgeting capability is used, then this field should be
initialized with data from a serial EEPROM.
Bit
Field
Field
Name
Type
Default
Value
Description
2:0 SWMODE RO HWINIT Switch Mode. These configuration pins determine the
PES24T3G2 switch operating mode.
0x0 - Normal Switch Mode
0x1 - Normal Switch Mode with Serial EEPROM initialization
0x2 through 0x7 - reserved
4:3 Reserved RO 0x0 Reserved field.