Renesas 89HPES24T3G2ZBAL, User Manual

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Notes
PES24T3G2 User Manual 3 - 1 February 22, 2012
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Chapter 3
Link Operation
Introduction
Link operation in the PES24T3G2 adheres to the PCI Express 2.0 Base Specification, supporting
speeds of 2.5 Gbps and 5.0 Gbps. The PES24T3G2 contains three x8 ports. The default link width of each
port is x8 and the SerDes lanes are statically assigned to a port. A full link retrain is defined as retraining of
a link that transitions through the Detect LTSSM state.
Polarity Inversion
Each port of the PES24T3G2 supports automatic polarity inversion as required by the PCIe specifica-
tion. Polarity inversion is a function of the receiver and not the transmitter. The transmitter never inverts its
data. During link training, the receiver examines symbols 6 through 15 of the TS1 and TS2 ordered sets for
inversion of the PExAP[n] and PExAN[n] signals. If an inversion is detected, then logic for the receiving lane
automatically inverts received data. Polarity inversion is a lane and not a link function. Therefore, it is
possible for some lanes of link to be inverted and for others to not be inverted.
Lane Reversal
The PCIe specification describes an optional lane reversal feature. The PES24T3G2 offers limited
support for the automatic lane reversal feature outlined in the PCIe specification. Lane reversal mapping for
the configuration supported by the PES24T3G2 is illustrated in Figure 3.1.