Renesas 89HPES24T3G2ZBAL, User Manual

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IDT JTAG Boundary Scan
PES24T3G2 User Manual 9 - 2 February 22, 2012
Notes
The TAP controller transitions from state to state, according to the value present on JTAG_TMS, as
sampled on the rising edge of JTAG_TCK. The Test-Logic Reset state can be reached either by asserting
JTAG_TRST_N or by applying a 1 to JTAG_TMS for five consecutive cycles of JTAG_TCK. A state diagram
for the TAP controller appears in Figure 9.2. The value next to state represent the value that must be
applied to JTAG_TMS on the next rising edge of JTAG_TCK, to transition in the direction of the associated
arrow.
Figure 9.2 State Diagram of PES24T3G2’s TAP Controller
Pin Name Type Description
JTAG_TRST_N Input JTAG RESET (active low)
Asynchronous reset for JTAG TAP controller (internal pull-up)
JTAG_TCK Input JTAG Clock
Test logic clock. JTAG_TMS and JTAG_TDI are sampled on the rising edge.
JTAG_TDO is output on the falling edge.
JTAG_TMS Input JTAG Mode Select. Requires an external pull-up.
Controls the state transitions for the TAP controller state machine (internal pull-up)
JTAG_TDI Input JTAG Input
Serial data input for BSC chain, Instruction Register, IDCODE register, and BYPASS
register (internal pull-up)
JTAG_TDO Output JTAG Output
Serial data out. Tri-stated except when shifting while in Shift-DR and SHIFT-IR TAP con-
troller states.
Table 9.1 JTAG Pin Descriptions
Test- Logic
Reset
Run-Test/
Idle Select-
DR-Scan
Capture-DR
Shift-DR
Exit1 -DR
Pause-DR
Exit2-DR
Select-
IR-Scan
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Exit2-IR
Update-DR Update-IR
1 1
0
0 0
1 1
0
0
1
1
0
1
0
1
0
0
1
1
1
0
0
1 1
0
1
0
1
1
0
0 0
0