Renesas 89HPES24T3G2ZBAL, User Manual

Page: 34 / 165

IDT Clocking, Reset and Initialization
PES24T3G2 User Manual 2 - 2 February 22, 2012
Notes
Reset
The PES24T3G2 defines four Conventional Reset categories: Fundamental reset, Hot Reset, Upstream
Secondary Bus Hot-Reset, and Downstream Secondary Bus Hot-Reset.
– A Fundamental Reset causes all logic in the PES24T3G2 to be returned to an initial state.
– A Hot Reset causes all logic in the PES24T3G2 to be returned to an initial state, but does not
cause the state of register fields denoted as “sticky” to be modified.
– An Upstream Secondary Bus Reset causes all devices on the virtual PCI bus to be hot reset
except the upstream port (i.e., upstream PCI to PCI bridge).
– A Downstream Secondary Bus Reset causes a hot reset to be propagated on the corresponding
external secondary bus link.
There are two sub-categories of Fundamental Reset: Cold reset and Warm reset. A Cold Reset occurs
following the PES24T3G2 being powered on and assertion of PERSTN. A Warm Reset is a Fundamental
Reset that occurs without removal of power.
Fundamental Reset
A Fundamental Reset may be initiated by any of the following conditions:
– A cold reset initiated by a power-on and the assertion of the PCI Express Reset (PERSTN) input
pin.
– A warm reset initiated by the assertion of the PCI Express Reset (PERSTN) input pin while power
is on.
– A warm reset initiated by the writing of a one to the Fundamental Reset (FRST) bit in the Switch
Control (SWCTL) register.
PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside
PES24T3G2 and initiates a PCI Express fundamental reset.
RSTHALT
2
I Reset Halt. When this signal is asserted during a PCI Express fun-
damental reset, PES24T3G2 executes the reset procedure and
remains in a reset state with the Master and Slave SMBuses active.
This allows software to read and write registers internal to the device
before normal device operation begins. The device exits the reset
state when the RSTHALT bit is cleared in the SWCTL register by an
SMBus master.
SWMODE[2:0] I Switch Mode. These configuration pins determine the PES24T3G2
switch operating mode.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 - through 0x7 Reserved
These pins should be static and not change following the negation of
PERSTN.
1.
MSMBSMODE is not available in the 19mm package, resulting in the master SMBus operating only at 400 KHz.
2.
RSTHALT is not available in the 19mm package.
Signal
May Be
Overridden
Description
Table 2.1 Boot Configuration Vector Signals