Renesas 89HPES24T3G2ZBAL, User Manual

Page: 150 / 165

IDT Configuration Registers
PES24T3G2 User Manual 8 - 68 February 22, 2012
Notes
PHYLCFG0 - Phy Link Configuration 0 (0x530)
Bit
Field
Field
Name
Type
Default
Value
Description
12:0 Reserved RO 0x0 Reserved field.
13 SCLINKEN RW 0x0
Sticky
Self Cross Link Enable. When this bit is set, crosslink training
of a port to itself is enabled (i.e., the serial transmit lines of the
port may be connected to the serial receive lines of the same
port).
This bit has no effect when the CLINKDIS bit in this register is
set to 0x1.
Please refer to section Crosslink on page 3-10 for further
details.
14 ILSCC RW Upstream:
0x1
Down-
stream:
0x0
Sticky
Initial Link Speed Change Control. This field determines
whether a port automatically initiates a speed change to Gen2
speed, if Gen2 speed is permissible, after initial entry to L0 from
Detect.
0x0 - (automatic) Automatically initiate speed change to Gen2
speed, if permissible, after the first entry to L0 from
Detect.
0x1 - (nochange) Do not automatically initiate a speed change
to Gen2 speed, stay in Gen1 speed.
18:15 Reserved RO 0x0 Reserved field.
21:19 TLW RW 0x7 Target Link Width. This field indicates the target link width
when doing dynamic upconfiguration or downconfiguration of
the link (section Dynamic Link Width Reconfiguration on page 3-
3).
0x0 - Target LInk Width = x1
0x1 - Target Link Width = x2
0x2 - Target Link Width = x4
0x3 - Target Link Width = x8
0x4 - Reserved
0x5 - Reserved
0x6 - Reserved
0x7 - Target Link Width = Maximum Link Width (MAXLNK-
WDTH in the PCIELCAP register)
When performing link width downconfiguration, the value in this
field must be less than the Negotiated Link Width (NLW) field in
the PCIELSTS register.
When performing link width upconfiguration, the value written
into the TLW field must be greater than the NLW field and less
than the ILW field in the PCIELSTS register.
Link width upconfiguration or downconfiguration takes effect
when the Link Retrain (LRET) bit in the PCIELCTL register is
set.
Software must not simultaneously change the Target Link
Speed (TLS) field in the PCIELCTL2 together with this field
before setting the LRET bit. When this occurs, the behavior of
the PHY is undefined.
This field takes on its default value when the link is fully
retrained (i.e., the PHY LTSSM of the corresponding port transi-
tions through the DETECT state).
31:22 Reserved RO 0x0 Reserved field.