Renesas 89HPES24T3G2ZBAL, User Manual

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IDT Configuration Registers
PES24T3G2 User Manual 8 - 19 February 22, 2012
Notes
INTRPIN - Interrupt PIN Register (0x03D)
BCTL - Bridge Control Register (0x03E)
Bit
Field
Field
Name
Type
Default
Value
Description
7:0 INTRPIN RWL 0x0 Interrupt Pin. Interrupt pin or legacy interrupt messages are not
used by the bridge by default. However, they can be used for hot-
plug by the downstream ports and to report memory errors by the
upstream port.
This field should only be configured with values of 0x0 through
0x4. The PES24T3G2 bridges may only be configured to gener-
ate INTA interrupts. Therefore, correct values for this field are
only 0x0 and 0x1.
0x0 - (none) Bridge does not generate any interrupts.
0x1 - (INTA) Bridge generates INTA interrupts.
0x2 - (INTB) Bridge generates INTB interrupts.
0x3 - (INTC) Bridge generates INTC interrupts.
0x4 - (INTD) Bridge generates INTD interrupts.
Bit
Field
Field
Name
Type
Default
Value
Description
0 PERRE RW 0x0 Parity Error Response Enable. Not applicable.
1 SERRE RW 0x0 System Error Enable. This bit controls forwarding of ERR_COR,
ERR_NONFATAL, ERR_FATAL from the secondary interface of
the bridge to the primary interface.
Note that error reporting must be enabled in the Command regis-
ter or PCI Express Capability structure, Device Control register
for errors to be reported on the primary interface.
0x0 - (ignore) Do not forward errors from the secondary to the pri-
mary interface.
0x1 - (report) Enable forwarding of errors from secondary to the
primary interface.
2 ISAEN RW 0x0 ISA Enable. This bit controls the routing of ISA I/O transactions.
0 - (disable) Forward downstream all I/O addresses in the
address range defined by the I/O base and I/O limit registers
1 -(enable) Forward upstream ISA I/O addresses in the address
range defined by the I/O base and I/O limit registers that are in
the first 64 KB of PCI I/O address space (top 768 bytes of
each 1-KB block)
3 VGAEN RW 0x0 VGA Enable. Controls the routing of processor-initiated transac-
tions targeting VGA.
0 - (block) Do not forward VGA compatible addresses from the
primary interface to the secondary interface
1 - (forward) Forward VGA compatible addresses from the pri-
mary to the secondary interface.