Renesas 89HPES24T3G2ZBAL, User Manual

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IDT PES24T3G2 Device Overview
PES24T3G2 User Manual 1 - 11 February 22, 2012
Notes
Port Configuration
The PES24T3G2 operates as a 3-port switch with all ports having a x8 width, as shown in Figure 1.3.
Figure 1.3 PES24T3G2 Port Configuration
EJTAG / JTAG JTAG_TCK I LVTTL STI pull-up
JTAG_TDI I STI pull-up
JTAG_TDO O
JTAG_TMS I STI pull-up
JTAG_TRST_N I STI pull-up
SerDes Refer-
ence Resistors REFRES0 I/O Analog
REFRES1 I/O
REFRES2 I/O
REFRES3 I/O
REFRES4 I/O
REFRES5 I/O
1.
Internal resistor values under typical operating conditions are 92K
Ω
for pull-up and 90K
Ω
for pull-down.
2.
All receiver pins set the DC common mode voltage to ground. All transmitters must be AC coupled to the media.
3.
REFCLKM pin is not available in the 19mm package.
4.
SMBus address pins are not available in the 19mm package.
5.
Schmitt Trigger Input (STI).
6.
GPIO pins 3, 4, 5, 6 are not available in the 19mm package.
7.
MSMBSMODE and RSTHALT are not available in the 19mm package.
Function Pin Name Type Buffer
I/O
Type
Internal
Resistor
1
Notes
Table 1.9 Pin Characteristics (Part 2 of 2)
PES24T3G2
PCI to PCI
Bridge
PCI to PCI
Bridge
Dev. 2
PCI to PCI
Bridge
Dev. 4
Dev. 0
Port 0
Virtual PCI Bus
x8
Port 2
x8
Port 4
x8