MS51
Dec. 17, 2019
Page
83
of 316
Rev 1.01
M
S51
SE
RIES
TE
CHNICA
L REF
ERE
N
CE MA
NU
A
L
PnS
– Port n Schmitt Triggered Input
Regiser
Address
Reset Value
P0S
99H, Page 1
0000_0000 b
P1S
9BH, Page1
0000_0000 b
P3S
ACH, Page1
0000_0000 b
7
6
5
4
3
2
1
0
P0S.7
P0S.6
P0S.5
P0S.4
P0S.3
P0S.2
P0S.1
P0S.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Name
Description
n
P0S.n
P0.n Schmitt triggered input
0 = TTL level input of P0.n.
1 = Schmitt triggered input of P0.n.