MS51
Dec. 17, 2019
Page
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of 316
Rev 1.01
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6.6
Watchdog Timer (WDT)
The MS51 provides one Watchdog Timer (WDT). It can be configured as a time-out reset timer to
reset whole device. Once the device runs in an abnormal status or hangs up by outward interference,
a WDT reset recover the system. It provides a system monitor, which improves the reliability of the
system. Therefore, WDT is especially useful for system that is susceptible to noise, power glitches, or
electrostatic discharge. The WDT also can be configured as a general purpose timer, of which the
periodic interrupt serves as an event timer or a durational system supervisor in a monitoring system,
which is able to operate during Idle or Power-down mode. WDTEN[3:0] (CONFIG4[7:4]) initialize the
WDT to operate as a time-out reset timer or a general purpose timer.
CONFIG4
7
6
5
4
3
2
1
0
WDTEN[3:0]
-
-
-
-
R/W
-
-
-
-
Factory default value: 1111 1111b
Bit
Name
Description
7:4
WDTEN[3:0]
WDT enable
This field configures the WDT behavior after MCU execution.
1111 = WDT is Disabled. WDT can be used as a general purpose timer via software control.
0101 = WDT is Enabled as a time-out reset timer and it stops running during Idle or Power-
down mode.
Others = WDT is Enabled as a time-out reset timer and it keeps running during Idle or Power-
down mode.
The WDT is implemented with a set of divider that divides the low-speed internal oscillator clock
nominal 10kHz. The divider output is selectable and determines the time-out interval. When the time-
out interval is fulfilled, it will wake the system up from Idle or Power-down mode and an interrupt event
will occur if WDT interrupt is enabled. If WDT is initialized as a time-out reset timer, a system reset will
occur after a period of delay if without any software action.
The Watchdog time-out interval is determined by the formula
64
×
scalar
divider
clock
×
F
1
LIRC
, where
F
LIRC
is the frequency of internal 10 kHz oscillator. The following table shows an example of the
Watchdog time-out interval with different pre-scales.
WDPS.2
WDPS.1
WDPS.0
Clock Divider Scale
WDT Time-Out Timing
[1]
0
0
0
1/1
6.40 ms
0
0
1
1/4
25.60 ms
0
1
0
1/8
51.20 ms
0
1
1
1/16
102.40 ms
1
0
0
1/32
204.80 ms
1
0
1
1/64
409.60 ms
1
1
0
1/128
819.20 ms
1
1
1
1/256
1.638 s
Note:
This is an approximate value since the deviation of LIRC.
Table 6.6-1 Watchdog Timer-out Interval Under Different Pre-scalars
Since the limitation of the maxima vaule of WDT timer delay. To up MS51 from idle mode or power
