MS51
Dec. 17, 2019
Page
62
of 316
Rev 1.01
M
S51
SE
RIES
TE
CHNICA
L REF
ERE
N
CE MA
NU
A
L
CKEN
– Clock Enable
Regiser
Address
Reset Value
CKEN
97H, all pages, TA protected
0011_0000b
7
6
5
4
3
2
1
0
EXTEN[1:0]
HIRCEN
-
-
-
-
CKSWTF
R/W
R/W
-
-
-
-
R
Bit
Name
Description
7:6
EXTEN[1:0]
External clock source enable
11 = External clock input via X
IN
Enabled.
Others = external clock input is disable. P30 work as general purpose I/O.
5
HIRCEN
High-speed internal oscillator 16 MHz enable
0 = The high-speed internal oscillator Disabled.
1 = The high-speed internal oscillator Enabled.
Note that once IAP is enabled by setting IAPEN (CHPCON.0), the high-speed internal 16 MHz
oscillator will be enabled automatically. The hardware will also set HIRCEN and HIRCST bits.
After IAPEN is cleared, HIRCEN and EHRCST resume the original values.
4:1
-
Reserved
0
CKSWTF
Clock switch fault flag
0 = The previous system clock source switch was successful.
1 = User tried to switch to an instable or disabled clock source at the previous system clock
source switch. If switching to an instable clock source, this bit remains 1 until the clock
source is stable and switching is successful.
