MS51
Dec. 17, 2019
Page
164
of 316
Rev 1.01
M
S51
SE
RIES
TE
CHNICA
L REF
ERE
N
CE MA
NU
A
L
CHPCON
– Chip Control
Regiser
Address
Reset Value
CHPCON
9FH, all pages,TA protected
Software: 0000_00U0b
Others 0000_00C0b
7
6
5
4
3
2
1
0
SWRST
IAPFF
-
-
-
-
BS
IAPEN
W
R/W
-
-
-
-
R/W
R/W
Bit
Name
Description
7
SWRST
Software reset
To set this bit as logic 1 will cause a software reset. It will automatically be cleared via hardware
after reset is finished.
AUXR1
– Auxiliary Register 1
Regiser
Address
Reset Value
AUXR1
A2H, all pages
POR 0000_0000b,
Software 1U00_0000b
nRESET pin U100_0000b
Others UUU0_0000b
7
6
5
4
3
2
1
0
SWRF
RSTPINF
HardF
SLOW
GF2
UART0PX
0
DPS
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
Bit
Name
Description
7
SWRF
Software reset flag
When the MCU is reset via software reset, this bit will be set via hardware. It is recommended
that the flag be cleared via software.
6.2.9
Boot Select
RST pin reset
Brown-out reset
Software reset
Low voltage reset
Load
Reset and boot from LDROM
Reset and boot from APROM
CONFIG0.7
CHPCON.1
Watchdog timer reset
BS
CBS
BS = 0
BS = 1
Hard fault reset
Power-on reset
Figure 6.2-2 Boot Selecting Diagram
The MS51 provides user a flexible boot selection for variant application. The SFR bit BS in
CHPCON.1 determines MCU booting from APROM or LDROM after any source of reset. If reset