MS51
Dec. 17, 2019
Page
156
of 316
Rev 1.01
M
S51
SE
RIES
TE
CHNICA
L REF
ERE
N
CE MA
NU
A
L
CKEN
– Clock Enable
Regiser
Address
Reset Value
CKEN
97H, all pages, TA protected
0011_0000b
7
6
5
4
3
2
1
0
EXTEN[1:0]
HIRCEN
-
-
-
-
CKSWTF
R/W
R/W
-
-
-
-
R
Bit
Name
Description
7:6
EXTEN[1:0]
External clock source enable
11 = External clock input via X
IN
Enabled.
Others = external clock input is disable. P30 work as general purpose I/O.
5
HIRCEN
High-speed internal oscillator 16 MHz enable
0 = The high-speed internal oscillator Disabled.
1 = The high-speed internal oscillator Enabled.
Note that once IAP is enabled by setting IAPEN (CHPCON.0), the high-speed internal 16 MHz
oscillator will be enabled automatically. The hardware will also set HIRCEN and HIRCST bits.
After IAPEN is cleared, HIRCEN and EHRCST resume the original values.
4:1
-
Reserved
0
CKSWTF
Clock switch fault flag
0 = The previous system clock source switch was successful.
1 = User tried to switch to an instable or disabled clock source at the previous system clock
source switch. If switching to an instable clock source, this bit remains 1 until the clock
source is stable and switching is successful.
System Clock Divider
6.2.1.4
The oscillator frequency (F
OSC
) can be divided down, by an integer, up to 1/510 by configuring a
dividing register, CKDIV, to provide the system clock (F
SYS
). This feature makes it possible to
temporarily run the MCU at a lower rate, reducing power consumption. By dividing the clock, the MCU
can retain the ability to respond to events other than those that can cause interrupts (i.e. events that
allow exiting the Idle mode) by executing its normal program at a lower rate. This can often result in
lower power consumption than in Idle mode. This can allow bypassing the oscillator start-up time in
cases where Power-down mode would otherwise be used. The value of CKDIV may be changed by
the program at any time without interrupting code execution.
