MS51
Dec. 17, 2019
Page
198
of 316
Rev 1.01
M
S51
SE
RIES
TE
CHNICA
L REF
ERE
N
CE MA
NU
A
L
Bit
Name
Description
3
T1OE
Timer 1 output enable
0 = Timer 1 output Disabled.
1 = Timer 1 output Enabled from T1 pin.
Note that Timer 1 output should be enabled only when operating in its “Timer” mode.
2
T0OE
Timer 0 output enable
0 = Timer 0 output Disabled.
1 = Timer 0 output Enabled from T0 pin.
Note that Timer 0 output should be enabled only when operating in its
“Timer” mode.
0
P2S.0
P2.0 Schmitt triggered input
0 = TTL level input of P2.0.
1 = Schmitt triggered input of P2.0.
Output Slew Rate Control
6.4.2.4
Slew rate for each I/O pin is configurable individually. By default, each pin is in normal slew rate mode.
User can set each control register bit to enable high-speed slew rate for the corresponding I/O pin.
Note that all PxSR registers are accessible by switching SFR page to Page 1.
PnSR
–Port n Slew Rate Control
Register
SFR Address
Reset Value
P0SR
82H, Page 1
0000_0000 b
P1SR
84H, Page 1
0000_0000 b
P3SR
ADH, Page 1
0000_0000 b
7
6
5
4
3
2
1
0
PnSR.7
PnSR.6
PnSR.5
PnSR.4
PnSR.3
PnSR.2
PnSR.1
PnSR.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Name
Description
7:0
PnSR[7:0]
P0.n slew rate
0 = Pn.x normal output slew rate.
1 = Pn.x high-speed output slew rate.
6.4.3
Read-Modify-Write Instructions
Instructions that read a byte from SFR or internal RAM, modify it, and rewrite it back, are called “Read-
Modify-
Write” instructions. When the destination is an I/O port or a port bit, these instructions read the
internal output latch rather than the external pin state. This kind of instructions read the port SFR
value, modify it and write back to the port SFR. All “Read-Modify-Write” instructions are listed as
follows.
Instruction
Description
ANL
Logical AND. (ANL direct, A and ANL direct, #data)
ORL
Logical OR. (ORL direct, A and ORL direct, #data)
XRL
Logical exclusive OR. (XRL direct, A and XRL direct, #data)
JBC
Jump if bit = 1 and clear it. (JBC bit, rel)
CPL
Complement bit. (CPL bit)