MS51
Dec. 17, 2019
Page
135
of 316
Rev 1.01
M
S51
SE
RIES
TE
CHNICA
L REF
ERE
N
CE MA
NU
A
L
EIP
– Extensive Interrupt Priority
Regiser
Address
Reset Value
EIP
EFH, all pages
0000_0000b
7
6
5
4
3
2
1
0
PT2
PSPI
PFB
PWDT
PPWM
PCAP
PPI
PI2C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Name
Description
7
PT2
Timer 2 interrupt priority low bit
6
PSPI
SPI interrupt priority low bit
5
PFB
Fault Brake interrupt priority low bit
4
PWDT
WDT interrupt priority low bit
3
PPWM
PWM interrupt priority low bit
2
PCAP
Input capture interrupt priority low bit
1
PPI
Pin interrupt priority low bit
0
PI2C
I
2
C interrupt priority low bit
Note:
EIP is used in combination with the EIPH to determine the priority of each interrupt source. See Table 6.2-2 Interrupt
Priority Level Setting for correct interrupt priority configuration.
