MS51
Dec. 17, 2019
Page
287
of 316
Rev 1.01
M
S51
SE
RIES
TE
CHNICA
L REF
ERE
N
CE MA
NU
A
L
PWMP (2nd)
PWMP (1st)
PWM01 (2nd)
PWM01 (1st)
PG01 output
Load
PWM01 (2nd)
Load
PWMP (2nd)
PWM01 (2nd)
duty valid
PWMP (2nd) period valid
12-bit counter
Figure 6.11-4 PWM Center-aligned Type Waveform
The output frequency and duty cycle for center-aligned PWM are given by following equations:
PWM frequency =
}
,
{
2
PWMnPL
PWMnPH
F
PWM
(F
PWM
is the PWM clock source frequency divided by
PWMDIV).
PWM high level duty =
}
,
{
}
,
{
PWMnPL
PWMnPH
PWMnCHxL
PWMnCHxH
.
6.11.3
Operation Modes
After PGn signals pass through the first stage of the PWM and Fault Brake output control circuit. The
PWM mode selection circuit generates different kind of PWM output modes with six-channel, three-
pair signal PG0~PG5 . It supports independent mode, complementary mode, and synchronous mode.
Independent Mode
6.11.3.1
Independent mode is enabled when PWMMOD[1:0] (PWMnCON1[7:6]) is [0:0]. It is the default mode
of PWM. PG0, PG1, PG2, PG3, PG4 and PG5 output PWM signals independently.
Complementary Mode with Dead-Time Insertion
6.11.3.2
Complementary mode is enabled when PWMMOD[1:0] = [0:1]. In this mode, PG0/2/4 output PWM
signals the same as the independent mode. However, PG1/3/5 output the out-phase PWM signals of
PG0/2/4 correspondingly, and ignore PG1/3/5 Duty register {PWMnH, PWMnL} (n:1/3/5). This mode
makes PG0/PG1 a PWM complementary pair and so on PG2/PG3 and PG4/PG5.
In a real motor application, a comple
mentary PWM output always has a need of “dead-time” insertion
to prevent damage of the power switching device like GPIBs due to being active on simultaneously of
the upper and lower switches of the half bridge, even in a “μs” duration. For a power switch device
physically cannot switch on/off instantly. For the MS51 PWM, each PWM pair share a 9-bit dead-time
down-counter PWM0DTCNT used to produce the off time between two PWM signals in the same pair.
On implementation, a 0-to-1 signal edge delays after PWM0DTCNT timer underflows. The timing
diagram illustrates the complementary mode with dead-time insertion of PG0/PG1 pair. Pairs of
PG2/PG3 and PG4/PG5 have the same dead-time circuit. Each pair has its own dead-time enabling
bit in the field of PWMnDTEN [3:0].
Note that the PWM0DTCNT and PWMnDTEN registers are all TA write protection. The dead-time
control are also valid only when the PWM is configured in its complementary mode.
