MS51
Dec. 17, 2019
Page
295
of 316
Rev 1.01
M
S51
SE
RIES
TE
CHNICA
L REF
ERE
N
CE MA
NU
A
L
Regiser
Address
Reset Value
PMEN
FBH, all page
0000_0000b
7
6
5
4
3
2
1
0
-
-
PMEN5
PMEN4
PMEN3
PMEN2
PMEN1
PMEN0
-
-
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Name
Description
n
PMENn
PWMn mask enable
0 = PWMn signal outputs from its PWM generator.
1 = PWMn signal is masked by PMDn.
PMD
– PWM Mask Data
Regiser
Address
Reset Value
PMD
FCH, all page
0000_0000b
7
6
5
4
3
2
1
0
-
-
PMD5
PMD4
PMD3
PMD2
PMD1
PMD0
-
-
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Name
Description
n
PMDn
PWMn mask data
The PWMn signal outputs mask data once its corresponding PMENn is set.
0 = PWMn signal is masked by 0.
1 = PWMn signal is masked by 1.
FBD
– PWM Fault Brake Data
Regiser
Address
Reset Value
FBD
D7H, all pages
0000_0000b
7
6
5
4
3
2
1
0
FBF
FBINLS
FBD5
FBD4
FBD3
FBD2
FBD1
FBD0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Name
Description
7
FBF
Fault Brake flag
This flag is set when FBINEN is set as 1 and FB pin detects an edge, which matches FBINLS
(FBD.6) selection. This bit is cleared by software. After FBF is cleared, Fault Brake data output will
not be released until PWMRUN (PWMCON0.7) is set.
6
FBINLS
FB pin input level selection
0 = Falling edge.
1 = Rising edge.
5:0
FBDn
PWMn Fault Brake data
0 = PWMn signal is overwritten by 0 once Fault Brake asserted.
1 = PWMn signal is overwritten by 1 once Fault Brake asserted.
PNP
– PWM Negative Polarity
