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MS51
Dec. 17, 2019
Page
301
of 316
Rev 1.01
M
S51
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CHNICA
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CE MA
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A
L
Bit
Name
Description
3:0
ADCHS[3:0]
A/D converting channel select
This filed selects the activating analog input source of ADC. If ADCEN is 0, all inputs are
disconnected.
0000 = ADC_CH0.
0001 = ADC_CH1.
0010 = ADC_CH2.
0011 = ADC_CH3.
0100 = ADC_CH4.
0101 = ADC_CH5.
0110 = ADC_CH6.
0111 = ADC_CH7
1000 = Internal band-gap voltage.
Others = Reserved.
ADCCON1
– ADC Control 1
Regiser
Address
Reset Value
ADCCON1
E1H, page 0
0000_0000b
7
6
5
4
3
2
1
0
OCEN
STADCPX
ADCDIV[1:0]
ETGTYP[1:0]
ADCEX
ADCEN
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Name
Description
6
STADCPX
External start ADC trigger pin select
0 = Assign STADC to P0.4.
1 = Assign STADC to P1.3.
Note that STADC will exchange immediately once setting or clearing this bit.
5:4
ADCDIV[1:0]
ADC clock divider
00 = ADC clock source = F
SYS
/1.
01 = ADC clock source = F
SYS
/2.
10 = ADC clock source = F
SYS
/4.
11 = ADC clock source = F
SYS
/8.
3:2
ETGTYP[1:0]
External trigger type select
When ADCEX (ADCCON1.1) is set, these bits select which condition triggers ADC
conversion.
00 = Falling edge on PWM0 channel 0/2/4 or STADC pin.
01 = Rising edge on PWM0 channel 0/2/4 or STADC pin.
10 = Central point of a PWM0 period.
11 = End point of a PWM0 period.
Note that the central point interrupt or the period point interrupt is only available for PWM
center-aligned type.
1
ADCEX
ADC external conversion trigger select
This bit select the methods of triggering an A/D conversion.
0 = A/D conversion is started only via setting ADCS bit.
1 = A/D conversion is started via setting ADCS bit or by external trigger source depending on
ETGSEL[1:0] and ETGTYP[1:0]. Note that while ADCS is 1 (busy in converting), the ADC will
ignore the following external trigger until ADCS is hardware cleared.
0
ADCEN
ADC enable
0 = ADC circuit off.
1 = ADC circuit on.
ADCCON2
– ADC Control 2
Regiser
Address
Reset Value
ADCCON2
E2H, page0
0000_0000b