MS51
Dec. 17, 2019
Page
88
of 316
Rev 1.01
M
S51
SE
RIES
TE
CHNICA
L REF
ERE
N
CE MA
NU
A
L
IP
– Interrupt Priority
Regiser
Address
Reset Value
IP
B8H, all pages, Bit addressable
0000_0000 b
7
6
5
4
3
2
1
0
-
PADC
PBOD
PS
PT1
PX1
PT0
PX0
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Name
Description
6
PADC
ADC interrupt priority low bit
5
PBOD
Brown-out detection interrupt priority low bit
4
PS
Serial port 0 interrupt priority low bit
3
PT1
Timer 1 interrupt priority low bit
2
PX1
External interrupt 1 priority low bit
1
PT0
Timer 0 interrupt priority low bit
0
PX0
External interrupt 0 priority low bit
Note:
IP is used in combination with the IPH to determine the priority of each interrupt source. See Table 6.2-2 Interrupt
Priority Level Setting for correct interrupt priority configuration.
