MS51
Dec. 17, 2019
Page
279
of 316
Rev 1.01
M
S51
SE
RIES
TE
CHNICA
L REF
ERE
N
CE MA
NU
A
L
Regiser
Address
Reset Value
I2TOC
BFH, all pages
0000_1001 b
7
6
5
4
3
2
1
0
-
-
-
-
-
I2TOCEN
DIV
I2TOF
-
-
-
-
-
R/W
R/W
R/W
Bit
Name
Description
2
I2TOCEN
I
2
C time-out counter enable
0 = I
2
C time-out counter Disabled.
1 = I
2
C time-out counter Enabled.
Note:
please always enable I
2
C interrupt when enable I
2
C time-out counter function
1
DIV
I
2
C time-out counter clock divider
0 = The clock of I
2
C time-out counter is F
SYS
/1.
1 = The clock of I
2
C time-out counter is F
SYS
/4.
0
I2TOF
I
2
C time-out flag
This flag is set by hardware if 14-bit I
2
C time-out counter overflows. It is cleared by software.
6.10.7
Typical Structure of I
2
C Interrupt Service Routine
The following software example in C language for KEIL
TM
C51 compiler shows the typical structure of
the I
2
C interrupt service routine including the 26 state service routines and may be used as a base for
user applications. User can follow or modify it for their own application. If one or more of the five
modes are not used, the associated state service routines may be removed, but care should be taken
that a deleted routine can never be invoked.
Void I2C_ISR (void) interrupt 6
{
switch (I2STAT)
{
//===============================================
//Bus Error, always put in ISR for noise handling
//===============================================
case 0x00:
/*00H, bus error occurs*/
STO = 1;
//recover from bus error
break;
//===========
//Master Mode
//===========
case 0x08:
/*08H, a START transmitted*/
STA = 0;
//STA bit should be cleared by software
I2DAT = SLA_ADDR1;
//load SLA+W/R
break;
case 0x10:
/*10H, a repeated START transmitted*/
STA = 0;
I2DAT = SLA_ADDR2;
break;
//=======================
//Master Transmitter Mode
//=======================
case 0x18:
/*18H, SLA+W transmitted, ACK received*/
I2DAT = NEXT_SEND_DATA1;
//load DATA
break;
