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Dec. 17, 2019
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6.2.13
Interrupt Priorities
There are four priority levels for all interrupts. They are level highest, high, low, and lowest; and they
are represented by level 3, level 2, level 1, and level 0. The interrupt sources can be individually set to
one of four priority levels by setting their own priority bits. Table 6.2-2 lists four priority setting.
Naturally, a low level priority interrupt can itself be interrupted by a high level priority interrupt, but not
by any same level interrupt or lower level. In addition, there exists a pre-defined natural priority among
the interrupts themselves. The natural priority comes into play when the interrupt controller has to
resolve simultaneous requests having the same priority level.
In case of multiple interrupts, the following rules apply:
1. While a low priority interrupt handler is running, if a high priority interrupt arrives, the handler will be
interrupted and the high priority handler will run. When the high priority handler does “RETI”, the low
priority handler will resume. When this handler does “RETI”, control is passed back to the main
program.
2. If a high priority interrupt is running, it cannot be interrupted by any other source
– even if it is a high
priority interrupt which is higher in natural priority.
3. A low-priority interrupt handler will be invoked only if no other interrupt is already executing. Again,
the low priority interrupt cannot preempt another low priority interrupt, even if the later one is higher in
natural priority.
4. If two interrupts occur at the same time, the interrupt with higher priority will execute first. If both
interrupts are of the same priority, the interrupt which is higher in natural priority will be executed first.
This is the only context in which the natural priority matters.
This natural priority is defined as shown on Table 6.2-2 Interrupt Priority Level Setting
. It also summarizes the interrupt sources, flag bits, vector addresses, enable bits, priority bits, natural
priority and the permission to wake up the CPU from Power-down mode. For details of waking CPU up
from Power-down mode, please see Section 6.2.2.2
Interrupt Priority Control Bits
Interrupt Priority Level
IPH / EIPH / EIPH1
IP / EIP / EIP2
0
0
Level 0 (lowest)
0
1
Level 1
1
0
Level 2
1
1
Level 3 (highest)
Table 6.2-2 Interrupt Priority Level Setting
Interrupt Source
Vector
Address
Interrupt Flag(S)
Enable Bit
Natural
Priority
Priority Control
Bits
Power-Down
Wake-Up
Reset
0000H
-
Always
Enabled
Highest
-
Yes
External interrupt 0
0003H
IE0[1]
EX0
1
PX0, PX0H
Yes
Brown-out
0043H
BOF (BODCON0.3)
EBOD
2
PBOD, PBODH
Yes
Watchdog Timer
0053H
WDTF (WDCON.5)
EWDT
3
PWDT, PWDTH
Yes
Timer 0
000BH
TF0[2]
ET0
4
PT0, PT0H
No
I2C status/time-out
0033h
SI + I2TOF (I2TOC.0)
EI2C
5
PI2C, PI2CH
No
ADC
005Bh
ADCF
EADC
6
PADC, PADCH
No
External interrupt 1
0013H
IE1[1]
EX1
7
PX1, PX1H
Yes
Pin interrupt
003BH
PIF0 to PIF7 (PIF)[3]
EPI
8
PPI, PPIH
Yes
