MS51
Dec. 17, 2019
Page
263
of 316
Rev 1.01
M
S51
SE
RIES
TE
CHNICA
L REF
ERE
N
CE MA
NU
A
L
Bit
Name
Description
7:2
-
Reserved
1:0
SPIS[1:0] SPI Interval time selection between adjacent bytes
SPIS[1:0] and CPHA select eight grades of SPI interval time selection between adjacent bytes. As
below table:
CPHA
SPIS1
SPIS0
SPI clock
0
0
0
0.5
0
0
1
1.0
0
1
0
1.5
0
1
1
2.0
1
0
0
1.0
1
0
1
1.5
1
1
0
2.0
1
1
1
2.5
SPIS[1:0] are valid only under Master mode (MSTR = 1).
SPSR
– Serial Peripheral Status Register
Regiser
Address
Reset Value
SPSR
F4H, all page
0000_0000b
7
6
5
4
3
2
1
0
SPIF
WCOL
SPIOVF
MODF
DISMODF
TXBUF
-
-
R/W
R/W
R/W
R/W
R/W
R
-
-
Bit
Name
Description
7
SPIF
SPI complete flag
This bit is set to logic 1 via hardware while an SPI data transfer is complete or an receiving data
has been moved into the SPI read buffer. If ESPI (EIE .0) and EA are enabled, an SPI interrupt will
be required. This bit should be cleared via software. Attempting to write to SPDR is inhibited if
SPIF is set.
6
WCOL
Write collision error flag
This bit indicates a write collision event. Once a write collision event occurs, this bit will be set. It
should be cleared via software.
5
SPIOVF
SPI overrun error flag
This bit indicates an overrun event. Once an overrun event occurs, this bit will be set. If ESPI and
EA are enabled, an SPI interrupt will be required. This bit should be cleared via software.
4
MODF
Mode Fault error flag
This bit indicates a Mode Fault error event. If
SS
̅̅̅̅
pin is configured as Mode Fault input (MSTR = 1
and DISMODF = 0) and
SS
̅̅̅̅
is pulled low by external devices, a Mode Fault error occurs. Instantly
MODF will be set as logic 1. If ESPI and EA are enabled, an SPI interrupt will be required. This bit
should be cleared via software.
3
DISMODF
Disable Mode Fault error detection
This bit is used in combination with the SSOE (SPCR.7) bit to determine the feature of
SS
̅̅̅̅
pin as
shown in Table 6.9-1 Slave Select Pin Configurations. DISMODF is valid only in Master mode
(MSTR = 1).
0 = Mode Fault detection Enabled.
SS
̅̅̅̅
serves as input pin for Mode Fault detection disregard of
SSOE.
1 = Mode Fault detection Disabled. The feature of
SS
̅̅̅̅
follows SSOE bit.
