MS51
Dec. 17, 2019
Page
303
of 316
Rev 1.01
M
S51
SE
RIES
TE
CHNICA
L REF
ERE
N
CE MA
NU
A
L
ADCDLY
– ADC Trigger Delay Counter
Regiser
Address
Reset Value
ADCDLY
E3H, all pages
0000_0000b
7
6
5
4
3
2
1
0
ADCDLY[7:0]
R/W
Bit
Name
Description
7:0
ADCDLY[7:0]
ADC external trigger delay counter low byte
This 8-bit field combined with ADCCON2.0 forms a 9-bit counter. This counter inserts a delay
after detecting the external trigger. An A/D converting starts after this period of delay.
External trigger delay time =
ADC
F
ADCDLY
.
Note that this field is valid only when ADCEX (ADCCON1.1) is set. User should not modify
ADCDLY during PWM run time if selecting PWM output as the external ADC trigger source.
ADCRH
– ADC Result High Byte
Regiser
Address
Reset Value
ADCRH
C3H, page 0
0000_0000b
7
6
5
4
3
2
1
0
ADCR[11:4]
R
Bit
Name
Description
7:0
ADCR[11:4]
ADC result high byte
The most significant 8 bits of the ADC result stored in this register.
ADCRL
– ADC Result Low Byte
Regiser
Address
Reset Value
ADCRL
C2H, page 0
0000_0000b
7
6
5
4
3
2
1
0
-
-
-
-
ADCR[3:0]
-
-
-
-
R
Bit
Name
Description
3:0
ADCR[3:0]
ADC result low byte
The least significant 4 bits of the ADC result stored in this register.
