MS51
Dec. 17, 2019
Page
121
of 316
Rev 1.01
M
S51
SE
RIES
TE
CHNICA
L REF
ERE
N
CE MA
NU
A
L
PWMnL
– PWM0 Duty Low Byte
Regiser
Address
Reset Value
PWM0L
DAH, all pages
0000 _0000 b
PWM1L
DBH, all pages
0000 _0000 b
PWM2L
DCH, all pages
0000 _0000 b
PWM3L
DDH, all pages
0000 _0000 b
PWM4L
CCH, Page 1
0000 _0000 b
PWM5L
CCH, Page 1
0000 _0000 b
7
6
5
4
3
2
1
0
PWM0[7:0]
R/W
Bit
Name
Description
7:0
PWM0[7:0]
PWM0 Channel 0 duty low byte
This byte with PWM0H controls the duty of the output signal PG0 from PWM generator.
