MS51
Dec. 17, 2019
Page
182
of 316
Rev 1.01
M
S51
SE
RIES
TE
CHNICA
L REF
ERE
N
CE MA
NU
A
L
Bit
Name
Description
0
IAPEN
IAP enable
0 = IAP function Disabled.
1 = IAP function Enabled.
Once enabling IAP function, the HIRC will be turned on for timing control. To clear IAPEN should
always be the last instruction after IAP operation to stop internal oscillator if reducing power
consumption is concerned.
IAPUEN
– IAP Updating Enable
Regiser
Address
Reset Value
IAPUEN
A5H, all pages,TA protected
0000_0000b
7
6
5
4
3
2
1
0
-
-
-
SPMEN
SPUEN
CFUEN
LDUEN
APUEN
-
-
-
R/W
R/W
R/W
R/W
R/W
Bit
Name
Description
7:5
-
Reserved
4
SPMEN
SPROM Memory space mapping enable
0 = CPU memory address 0xff80~0xffff is mapping to APROM memory
1 = CPU memory address 0xff80~0xffff is mapping to SPROM memory
3
SPUEN
SPROM Memory space updated enable(TA protected)
0 = Inhibit erasing or programming SPROM bytes by IAP
1 = Allow erasing or programming SPROM bytes by IAP.
2
CFUEN
CONFIG bytes updated enable
0 = Inhibit erasing or programming CONFIG bytes by IAP.
1 = Allow erasing or programming CONFIG bytes by IAP.
1
LDUEN
LDROM updated enable
0 = Inhibit erasing or programming LDROM by IAP.
1 = Allow erasing or programming LDROM by IAP.
0
APUEN
APROM updated enable
0 = Inhibit erasing or programming APROM by IAP.
1 = Allow erasing or programming APROM by IAP.
IAPCN
– IAP Control
Regiser
Address
Reset Value
IAPCN
AFH, all pages
0011_0000b
7
6
5
4
3
2
1
0
IAPB[1:0]
FOEN
FCEN
FCTRL[3:0]
R/W
R/W
R/W
R/W
Bit
Name
Description
7:6
IAPB[1:0]
IAP control
This byte is used for IAP command. For details, see Table 6.3-1 IAP Modes and Command
Codes.
5
FOEN
4
FCEN
