MS51
Dec. 17, 2019
Page
311
of 316
Rev 1.01
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S51
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CHNICA
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8
INSTRUCTION SET
8.1
Instruction Set and Address Mode
The MS51 executes all the instructions of the standard 80C51 family fully compatible with MCS-51.
However, the timing of each instruction is different for it uses high performance 1T 8051 core. The
architecture eliminates redundant bus states and implements parallel execution of fetching, decode,
and execution phases. The MS51 uses one clock per machine-cycle. It leads to performance
improvement of rate 8.1 (in terms of MIPS) with respect to traditional 12T 80C51 device working at the
same clock frequency. However, the real speed improvement seen in any system will depend on the
instruction mix.
All instructions are coded within an 8-bit field called an OPCODE. This single byte should be fetched
from Program Memory. The OPCODE is decoded by the CPU. It determines what action the CPU will
take and whether more operation data is needed from memory. If no other data is needed, then only
one byte was required. Thus the instruction is called a one byte instruction. In some cases, more data
is needed, which is two or three byte instructions.
Instruction
CY
OV
AC
Instruction
CY
OV
AC
ADD
X
[1]
X
X
CLR C
0
ADDC
X
X
X
CPL C
X
SUBB
X
X
X
ANL C, bit
X
MUL
0
X
ANL C, /bit
X
DIV
0
X
ORL C, bit
X
DA A
X
ORL C, /bit
X
RRC A
X
MOV C, bit
X
RLC A
X
CJNE
X
SETB C
1
Note:
X indicates the modification depends on the result of the instruction.
Table 8.1-1 Instructions That Affect Flag Settings
Table 8.2-1 Instruction Set lists all instructions for details. The note of the instruction set and
addressing modes are shown below.
Rn (N = 0~7)
Register R0 To R7 Of The Currently Selected Register Bank.
Direct
8-bit
internal data location’s address. It could be an internal data RAM location (00H to 7FH) or an
SFR (80H to FFH).
@RI (I = 0, 1)
8-bit internal data RAM location (00H to FFH) addressed indirectly through register R0 or R1.
#data
8-bit constant included in the instruction.
#data16
16-bit constant included in the instruction.
Addr16
16-bit destination address. Used by LCALL and LJMP. A branch can be any-where within the
Program Memory address space.
Addr11
11-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2K-Byte
page of Program Memory as the first byte of the following instruction.
Rel
Signed (2’s complement) 8-bit offset Byte. Used by SJMP and all conditional branches. The range
is -128 to +127 bytes relative to first byte of the following instruction.
Bit
Direct addressed bit in internal data RAM or SFR.
