Nuvoton NuMicro MS51 Series Page 73 Technical Reference Manual Download

Page: 73 / 316

MS51

Dec. 17, 2019

Page

of 316

Rev 1.01

S51

SE
RIES

CHNICA

L REF

ERE

CE MA

IAPUEN

– IAP Updating Enable

Regiser

Address

Reset Value

IAPUEN

A5H, all pages,TA protected

0000_0000b

CFUEN

LDUEN

APUEN

R/W

Bit

Name

Description

CFUEN

CONFIG bytes updated enable
0 = Inhibit erasing or programming CONFIG bytes by IAP.
1 = Allow erasing or programming CONFIG bytes by IAP.

LDUEN

LDROM updated enable
0 = Inhibit erasing or programming LDROM by IAP.
1 = Allow erasing or programming LDROM by IAP.

APUEN

APROM updated enable
0 = Inhibit erasing or programming APROM by IAP.
1 = Allow erasing or programming APROM by IAP.

Summary of Contents for NuMicro MS51 Series

Page 1: ...intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton Nuvoton is providing this document only for reference purposes of NuMicro microcont...

Page 2: ...UNCTION DESCRIPTION 21 6 1 Memory Organization 21 6 1 1 Program Memory 21 6 1 2 Data Flash 23 6 1 3 Security Protection Memory SPROM 23 6 1 4 Config Bytes 23 6 1 5 Data Memory 28 6 1 6 Special Functio...

Page 3: ...6 1 Time Out Reset Timer 229 6 6 2 General Purpose Timer 229 6 7 Self Wake Up Timer WKT 232 6 8 Serial Port UART0 UART1 235 6 8 1 Operating Mode 235 6 8 2 Baud Rate 237 6 8 3 Framing Error Detection...

Page 4: ...terrupt 289 6 11 8Control Regsiter 289 6 12 12 Bit Analog To Digital Converter ADC 297 6 12 1ADC Operation 298 6 12 2ADC Conversion Triggered by External Source 298 6 12 3ADC Conversion Result Compara...

Page 5: ...Drain Mode Structure 195 Figure 6 4 5 Pin Interface Block Diagram 200 Figure 6 5 1 Timer Counters 0 and 1 in Mode 0 205 Figure 6 5 2 Timer Counters 0 and 1 in Mode 1 206 Figure 6 5 3 Timer Counters 0...

Page 6: ...nsmitter Mode 270 Figure 6 10 11 Flow and Status of Master Receiver Mode 271 Figure 6 10 12 Flow and Status of Slave Receiver Mode 272 Figure 6 10 13 Flow and Status of General Call Mode 273 Figure 6...

Page 7: ...ble 6 2 3 Characteristics of Each Interrupt Source 168 Table 6 3 1 IAP Modes and Command Codes 181 Table 6 4 1 Configuration for Different I O Modes 193 Table 6 6 1 Watchdog Timer out Interval Under D...

Page 8: ...Up to 18 general purpose I O two 16 bit Timers Counters 0 1 one 16 bit Timer2 with three channel input capture module one Watchdog Timer WDT one Self Wake up Timer WKT one 16 bit auto reload Timer3 f...

Page 9: ...ty protection memory SPROM Memories Flash 16 KBytes of APROM for User Code 4 3 2 1 Kbytes of Flash for loader LDROM configure from APROM for In System Programmable ISP Flash Memory accumulated with pa...

Page 10: ...from Power down or Idle mode and auto reload count value Supports Interrupt PWM Up To 6 output pins can be selected Supports maximum clock source frequency up to 24 MHz Supports independent mode for P...

Page 11: ...hold time programmable SPI 1 sets of SPI devices Supports Master or Slave mode operation Supports MSB first or LSB first transfer sequence slave mode up to 12 MHz GPIO Four I O modes Quasi bidirection...

Page 12: ...ch MSOP10 MS51DA9AE 8 1 4 12 4 5 2 1 1 7 ch TSSOP14 MS51XB9AE 16 1 4 18 4 6 2 1 1 8 ch QFN20 3 MS51XB9BE 16 1 4 18 4 6 2 1 1 8 ch QFN20 3 MS51FB9AE 16 1 4 18 4 6 2 1 1 8 ch TSSOP20 MS51FC0AE 32 2 4 18...

Page 13: ...ne Package Flash SRAM Reserve Temperature 1T 8051 Industry 51 Base B MSOP10 3x3 mm D TSSOP14 4 4x5 0 mm E TSSOP28 4 4x9 7 mm F TSSOP20 4 4x6 5 mm I SOP8 4x5 mm O SOP20 300 mil P LQFP32 7x7 mm T QFN33...

Page 14: ...VSS 18 19 16 17 14 15 12 13 11 20 VDD MS51FB9AE I2C0_SDA UART1_TXD ICE_DAT P1 6 P1 3 I2C0_SCL STADC P1 4 I2C0_SDA PWM0_BRAKE PWM0_CH1 P1 1 ADC_CH7 PWM0_CH1 IC1 CLKO P1 0 PWM0_CH2 IC2 SPI0_CLK P0 0 PW...

Page 15: ...sive choice not a duplication of the function PWM0_CH2 IC6 T0 ADC_CH4 P0 5 UART0_TXD ADC_CH3 P0 6 nRESET P2 0 INT0 OSCIN ADC_CH1 P3 0 ADC_CH5 STADC PWM0_CH3 IC3 P0 4 P0 3 PWM0_CH5 IC5 ADC_CH6 P0 2 ICE...

Page 16: ...duplication of the function P1 2 PWM0_CH0 IC0 P1 3 I2C0_SCL STADC P1 4 PWM0_CH1 I2C0_SDA PWM0_BRAKE P1 5 PWM0_CH5 IC7 SPI0_SS P1 1 PWM0_CH1 IC1 ADC_CH7 CLKO P1 0 PWM0_CH2 IC2 SPI0_CLK P0 0 PWM0_CH3 IC...

Page 17: ...M0 output channel 4 IC4 Input capture channel 4 SPI0_MISO SPI master input slave output 18 14 15 P0 2 Port 0 bit 2 ICE_CLK ICP OCD clock input UART1_RXD Serial port 1 receive input I2C0_SCL 3 I 2 C cl...

Page 18: ...put capture channel 1 ADC_CH7 ADC input channel 7 CLKO System clock output 13 9 10 P1 2 Port 1 bit 2 PWM0_CH0 PWM0 output channel 0 IC0 Input capture channel 0 12 11 9 P1 3 Port 1 bit 3 I2C0_SCL I 2 C...

Page 19: ...ND 5 17 12 P3 0 Port 3 bit 0 available when the internal oscillator is used as the system clock ADC_CH1 ADC input channel 1 INT0 External interrupt 0 input OSCIN If the ECLK mode is enabled Xin is the...

Page 20: ...s T1 P0 0 T0 P0 5 VDD GND 10 kHz Internal RC Oscillator LIRC 8 8 1 System Clock 6 Timer 2 with Input Capture IC0 IC7 FB P1 4 12 bit ADC ADC_CH0 ADC_CH7 8 STADC P1 3 or P0 4 Self Wake up Timer Timer 3...

Page 21: ...s the CPU to jump to that location with where it commences execution of the interrupt service routine ISR External Interrupt 0 for example is assigned to location 0003H If External Interrupt 0 is goin...

Page 22: ...is 16K Bytes 110 LDROM is 1K Bytes APROM is 15K Bytes 101 LDROM is 2K Bytes APROM is 14K Bytes 100 LDROM is 3K Bytes APROM is 13K Bytes 0xx LDROM is 4K Bytes APROM is 12K Bytes 1 The logic boundary ad...

Page 23: ...urity Mode 1 SPROM non secured mode the last byte is 0xFF The access behavior of SPROM is the same with APROM and LDROM All area can be read by CPU or ISP command and can be erased and programmed by I...

Page 24: ...2 RPD Reset pin disable 1 The reset function of P2 0 Nrst pin Enabled P2 0 Nrst functions as the external reset pin 0 The reset function of P2 0 Nrst pin Disabled P2 0 Nrst functions as an input only...

Page 25: ...0 LDSIZE 2 0 R W Factory default value 1111 1111b Bit Name Description 2 0 LDSIZE 2 0 LDROM size select 111 No LDROM APROM is 16 Kbytes 110 LDROM is 1 Kbytes APROM is 15 Kbytes 101 LDROM is 2 Kbytes...

Page 26: ...Brown out inhibiting IAP This bit decides whether IAP erasing or programming is inhibited by brown out status This bit is valid only when brown out detection is enabled 1 IAP erasing or programming is...

Page 27: ...WDTEN 3 0 WDT enable This field configures the WDT behavior after MCU execution 1111 WDT is Disabled WDT can be used as a general purpose timer via software control 0101 WDT is Enabled as a time out r...

Page 28: ...in all 80C51 devices The lowest 32 bytes as general purpose registers are grouped into 4 banks of 8 registers Program instructions call these registers as R0 to R7 Two bits RS0 and RS1 in the Program...

Page 29: ...37 3B 3A 39 38 3C 3D 3E 3F 43 42 41 40 44 45 46 47 4B 4A 49 48 4C 4D 4E 4F 53 52 51 50 54 55 56 57 5B 5A 59 58 5C 5D 5E 5F 63 62 61 60 64 65 66 67 6B 6A 69 68 6C 6D 6E 6F 73 72 71 70 74 75 76 77 7B 7A...

Page 30: ...Special Function Register SFR The MS51 uses Special Function Registers SFR to control and monitor peripherals and their modes The SFR reside in the register locations 80 to FFH and are accessed by dir...

Page 31: ...ERENCE MANUAL Bit Name Description 0 SFRPAGE SFR page select 0 Instructions access SFR page 0 1 Instructions access SFR page 1 Switch SFR page demo code MOV TA 0AAH switch to SFR page 1 MOV TA 55H MOV...

Page 32: ...proper operation of the system If leaving these control registers unprotected errant code may write undetermined value into them and results in incorrect operation and loss of control To prevent this...

Page 33: ...ter 4 clock cycles this window automatically closes Once the window closes the procedure should be repeated to write another protected bits Not that the TA protected SFR are required timed access for...

Page 34: ...B CAPCON3 CAPCON4 SPCR SPCR2 SPSR SPDR AINDIDS EIPH 1 0 E8 ADCCON0 PICON PINEN PIPEN PIF C2L C2H EIP 1 0 E0 ACC ADCCON1 ADCCON2 ADCDLY C0L C0H C1L C1H 1 0 D8 PWMCON0 PWMPL PWM0L PWM1L PWM2L PWM3L PIO...

Page 35: ...byte EEH C2H 7 0 0000 0000b C2L Input capture 2 low byte EDH C2L 7 0 0000 0000b PIF Pin interrupt flag ECH PIF7 PIF6 PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 0000 0000b PIPEN Pin interrupt high level rising edg...

Page 36: ...5 duty high byte C5H 1 PWM5 15 8 0000 0000b RL3 Timer 3 reload low byte C5H 0 RL3 7 0 0000 0000b PWM4H PWM4 duty high byte C4H 1 PWM4 15 8 0000 0000b T3CON Timer 3 control C4H 0 SMOD_1 SMOD0_1 BRCK T...

Page 37: ...APAL IAP address low byte A6H IAPA 7 0 0000 0000b IAPUEN 4 IAP update enable A5H CFUEN LDUEN APUEN 0000 0000b IAPTRG 4 IAP trigger A4H IAPGO 0000 0000b BODCON0 4 Brown out detection control 0 A3H BODE...

Page 38: ...Data pointer high byte 83H DPTR 15 8 0000 0000b DPL Data pointer low byte 82H DPTR 7 0 0000 0000b SP Stack pointer 81H SP 7 0 0000 0111b P0 Port 0 80H P0 7 P0 6 P0 5 P0 4 P0 3 P0 2 P0 1 P0 0 Output l...

Page 39: ...able Regiser Address Reset Value P0 80H all pages bit addressable 1111_1111 b P1 90H all pages bit addressable 1111_1111 b P2 A0H all pages bit addressable 0000_0001 b P3 B0H all pages bit addressable...

Page 40: ...nput only pin when RPD CONFIG0 2 is programmed as 0 When leaving RPD un programmed P2 0 is always read as 0 P3 Bit Name Description 0 P3 0 Port 3 bit 0 P3 0 is available only when the internal oscilla...

Page 41: ...all pages 0000_0111b 7 6 5 4 3 2 1 0 SP 7 0 R W Bit Name Description 7 0 SP 7 0 Stack pointer The Stack Pointer stores the scratch pad RAM address where the stack begins It is incremented before data...

Page 42: ...DPL 82H all pages 0000_0000b 7 6 5 4 3 2 1 0 DPL 7 0 R W Bit Name Description 7 0 DPL 7 0 Data pointer low byte This is the low byte of 16 bit data pointer DPL combined with DPH serve as a 16 bit data...

Page 43: ...PH 83H all pages 0000_0000b 7 6 5 4 3 2 1 0 DPH 7 0 R W Bit Name Description 7 0 DPH 7 0 Data pointer high byte This is the high byte of 16 bit data pointer DPH combined with DPL serve as a 16 bit dat...

Page 44: ...316 Rev 1 01 MS51 SERIES TECHNICAL REFERENCE MANUAL RCTRIM0 High Speed Internal Oscillator 16 MHz Trim 0 Regiser Address Reset Value RCTRIM0 84H all pages TA protected Default 16MHz HIRC value 7 6 5...

Page 45: ...Rev 1 01 MS51 SERIES TECHNICAL REFERENCE MANUAL RCTRIM1 High Speed Internal Oscillator 16 MHz Trim 1 Regiser Address Reset Value RCTRIM1 85H all pages TA protected default 16MHz HIRC value 7 6 5 4 3...

Page 46: ...Self Wake up Timer Reload Byte Regiser Address Reset Value RWK 86H all pages 0000_0000b 7 6 5 4 3 2 1 0 RWK 7 0 R W Bit Name Description 7 0 RWK 7 0 WKT reload byte It holds the 8 bit reload value of...

Page 47: ...that can be set or cleared by user via software 1 PD Power down mode Setting this bit puts CPU into Power down mode Under this mode both CPU and peripheral clocks stop and Program Counter PC suspends...

Page 48: ...s bit will halt Timer 0 and the current count will be preserved in TH0 and TL0 1 Timer 0 Enabled 3 IE1 External interrupt 1 edge flag If IT1 1 falling edge trigger this flag will be set by hardware wh...

Page 49: ...external pin T1 5 M1 Timer 1 mode select M1 M0 Timer 1 Mode 0 0 Mode 0 13 bit Timer Counter 0 1 Mode 1 16 bit Timer Counter 1 0 Mode 2 8 bit Timer Counter with auto reload from TH1 1 1 Mode 3 Timer 1...

Page 50: ...HNICAL REFERENCE MANUAL TL0 Timer 0 Low Byte Regiser Address Reset Value TL0 8AH all pages 0000_0000b 7 6 5 4 3 2 1 0 TL0 7 0 R W Bit Name Description 7 0 TL0 7 0 Timer 0 low byte The TL0 register is...

Page 51: ...HNICAL REFERENCE MANUAL TL1 Timer 1 Low Byte Regiser Address Reset Value TL1 8BH all pages 0000_0000b 7 6 5 4 3 2 1 0 TL1 7 0 R W Bit Name Description 7 0 TL1 7 0 Timer 1 low byte The TL1 register is...

Page 52: ...NICAL REFERENCE MANUAL TH0 Timer 0 High Byte Regiser Address Reset Value TH0 8CH all pages 0000_0000b 7 6 5 4 3 2 1 0 TH0 7 0 R W Bit Name Description 7 0 TH0 7 0 Timer 0 high byte The TH0 register is...

Page 53: ...NICAL REFERENCE MANUAL TH1 Timer 1 High Byte Regiser Address Reset Value TH1 8DH all pages 0000_0000b 7 6 5 4 3 2 1 0 TH1 7 0 R W Bit Name Description 7 0 TH1 7 0 Timer 1 high byte The TH1 register is...

Page 54: ...of PWM is the overflow of Timer 1 4 T1M Timer 1 clock mode select 0 The clock source of Timer 1 is the system clock divided by 12 It maintains standard 8051 compatibility 1 The clock source of Timer 1...

Page 55: ...interrupt are enabled setting this bit will make CPU execute WKT interrupt service routine This bit is not automatically cleared via hardware and should be cleared via software 3 WKTR WKT run control...

Page 56: ...ICAL REFERENCE MANUAL SFRS SFR Page Selection Regiser Address Reset Value SFRS 91H all pages TA protected 0000_0000b 7 6 5 4 3 2 1 0 SFRPAGE R W Bit Name Description 0 SFRPAGE SFR page select 0 Instru...

Page 57: ...able 0 Input capture channel 1 Disabled 1 Input capture channel 1 Enabled 4 CAPEN0 Input capture 0 enable 0 Input capture channel 0 Disabled 1 Input capture channel 0 Enabled 2 CAPF2 Input capture 2 f...

Page 58: ...1 0 CAP0LS 1 0 R W R W R W Bit Name Description 5 4 CAP2LS 1 0 Input capture 2 level select 00 Falling edge 01 Rising edge 10 Either Rising or falling edge 11 Reserved 3 2 CAP1LS 1 0 Input capture 1 l...

Page 59: ...6 ENF2 Enable noise filer on input capture 2 0 Noise filter on input capture channel 2 Disabled 1 Noise filter on input capture channel 2 Enabled 5 ENF1 Enable noise filer on input capture 1 0 Noise f...

Page 60: ...r Regiser Address Reset Value CKDIV 95H all pages 0000_0000b 7 6 5 4 3 2 1 0 CKDIV 7 0 R W Bit Name Description 7 0 CKDIV 7 0 Clock divider The system clock frequency FSYS follows the equation below a...

Page 61: ...not stable or disabled 1 High speed internal oscillator is enabled and stable 4 Reserved 3 ECLKST External clock input status 0 External clock input is not stable or disabled 1 External clock input is...

Page 62: ...h speed internal oscillator Disabled 1 The high speed internal oscillator Enabled Note that once IAP is enabled by setting IAPEN CHPCON 0 the high speed internal 16 MHz oscillator will be enabled auto...

Page 63: ...nly when the received 9 th bit is logic 1 and the received data matches Given or Broadcast address 4 REN Receiving enable 0 Serial port 0 reception Disabled 1 Serial port 0 reception Enabled in Mode 1...

Page 64: ...Name Description 7 0 SBUF 7 0 Serial port 0 data buffer This byte actually consists two separate registers One is the receiving resister and the other is the transmitting buffer When data is moved to...

Page 65: ...ame Description 7 0 SBUF_1 7 0 Serial port 1 data buffer This byte actually consists two separate registers One is the receiving resister and the other is the transmitting buffer When data is moved to...

Page 66: ...PSR 4 Enable 5 EFB Enable Fault Brake interrupt 0 Fault Brake interrupt Disabled 1 Interrupt generated by FBF FBD 7 Enabled 4 EWDT Enable WDT interrupt 0 WDT interrupt Disabled 1 Interrupt generated b...

Page 67: ...EWKT ET3 ES_1 R W R W R W Bit Name Description 2 EWKT Enable WKT interrupt 0 WKT interrupt Disabled 1 Interrupt generated by WKTF WKCON 4 Enabled 1 ET3 Enable Timer 3 interrupt 0 Timer 3 interrupt Dis...

Page 68: ...DTRF mirrored from WDCON 3 SWRF mirrored from AUXR1 7 R W R W R W R W R W R W Bit Name Description 7 6 Reserved 5 HardF mirrored from AUXR0 5 Clear this bit by write AUXR0 5 0 or RSR 5 0 4 POF mirrore...

Page 69: ...7 as 1 and BORST BODCON0 2 as 0 This bit should be cleared via software 0 IAPEN IAP enable 0 IAP function Disabled 1 IAP function Enabled Once enabling IAP function the HIRC will be turned on for tim...

Page 70: ...is recommended that the flag be cleared via software Note If MCU run in OCD debug mode and OCDEN 0 hard fault reset will be disabled and only HardF flag be asserted 4 SLOW ADC Slow Speed Selection Thi...

Page 71: ...E 2 and EA IE 7 are set a brown out interrupt requirement will be generated This bit should be cleared via software 2 BORST Brown out reset enable This bit decides whether a brown out reset is caused...

Page 72: ...P begins by setting this bit as logic 1 After this instruction the CPU holds the Program Counter PC and the IAP hardware automation takes over to control the progress After IAP action completed the Pr...

Page 73: ...N R W R W R W Bit Name Description 2 CFUEN CONFIG bytes updated enable 0 Inhibit erasing or programming CONFIG bytes by IAP 1 Allow erasing or programming CONFIG bytes by IAP 1 LDUEN LDROM updated ena...

Page 74: ...ES TECHNICAL REFERENCE MANUAL IAPAL IAP Address Low Byte Regiser Address Reset Value IAPAL A6H all pages 0000_0000b 7 6 5 4 3 2 1 0 IAPA 7 0 R W Bit Name Description 7 0 IAPA 7 0 IAP address low byte...

Page 75: ...TECHNICAL REFERENCE MANUAL IAPAH IAP Address High Byte Regiser Address Reset Value IAPAH A7H all pages 0000_0000b 7 6 5 4 3 2 1 0 IAPA 15 8 R W Bit Name Description 7 0 IAPA 15 8 IAP address high byte...

Page 76: ...rupt 0 ADC interrupt Disabled 1 Interrupt generated by ADCF ADCCON0 7 Enabled 5 EBOD Enable brown out interrupt 0 Brown out detection interrupt Disabled 1 Interrupt generated by BOF BODCON0 3 Enabled...

Page 77: ...e WDT counter starts running 6 WDCLR WDT clear Setting this bit will reset the WDT count to 00H It puts the counter in a known state and prohibit the system from unpredictable reset The meaning of wri...

Page 78: ...clock pre scalar select These bits determine the pre scale of WDT clock from 1 1 through 1 256 Note 1 WDTRF will be cleared after power on reset be set after WDT reset and remains unchanged after any...

Page 79: ...ing on BOD circuit every 6 4 ms periodically 11 BOD low power mode 3 by turning on BOD circuit every 25 6 ms periodically 0 BODFLT BOD filter control BOD has a filter which counts 32 clocks of FSYS to...

Page 80: ...0000_0000b 7 6 5 4 3 2 1 0 IAPFD 7 0 R W Bit Name Description 7 0 IAPFD 7 0 IAP flash data This byte contains flash data which is read from or is going to be written to the Flash Memory User should wr...

Page 81: ...ontrol Regiser Address Reset Value IAPCN AFH all pages 0011_0000b 7 6 5 4 3 2 1 0 IAPB 1 0 FOEN FCEN FCTRL 3 0 R W R W R W R W Bit Name Description 7 6 IAPB 1 0 IAP control This byte is used for IAP c...

Page 82: ...b P1M1 B3H Page 0 1111_1111 b P3M1 ACH Page 1 1111_1111 b 7 6 5 4 3 2 1 0 PnM1 7 PnM1 6 PnM1 5 PnM1 4 PnM1 3 PnM1 2 PnM1 1 PnM1 0 R W R W R W R W R W R W R W R W Bit Name Description 7 0 P0M1 7 0 Por...

Page 83: ...iser Address Reset Value P0S 99H Page 1 0000_0000 b P1S 9BH Page1 0000_0000 b P3S ACH Page1 0000_0000 b 7 6 5 4 3 2 1 0 P0S 7 P0S 6 P0S 5 P0S 4 P0S 3 P0S 2 P0S 1 P0S 0 R W R W R W R W R W R W R W R W...

Page 84: ...ess Reset Value P0SR B2H Page 1 0000_0000 b P1SR B4H Page 1 0000_0000 b P3SR ADH Page 1 0000_0000 b 7 6 5 4 3 2 1 0 P0SR 7 P0SR 6 P0SR 5 P0SR 4 P0SR 3 P0SR 2 P0SR 1 P0SR 0 R W R W R W R W R W R W R W...

Page 85: ...lid only when RPD CONFIG0 2 is programmed as 0 When selecting as a pin the pull up is always enabled 3 T1OE Timer 1 output enable 0 Timer 1 output Disabled 1 Timer 1 output Enabled from T1 pin Note th...

Page 86: ...high bit 5 PBOD Brown out detection interrupt priority high bit 4 PSH Serial port 0 interrupt priority high bit 3 PT1H Timer 1 interrupt priority high bit 2 PX1H External interrupt 1 priority high bi...

Page 87: ...edge on PWM0 channel 0 1 2 3 4 5 pin 01 Rising edge on PWM0 channel 0 1 2 3 4 5 pin 10 Central point of a PWM0 period 11 End point of a PWM0 period Note that the central point interrupt or the end po...

Page 88: ...errupt priority low bit 5 PBOD Brown out detection interrupt priority low bit 4 PS Serial port 0 interrupt priority low bit 3 PT1 Timer 1 interrupt priority low bit 2 PX1 External interrupt 1 priority...

Page 89: ...et Value SADEN B9H all pages 0000_0000 b 7 6 5 4 3 2 1 0 SADEN 7 0 R W Bit Name Description 7 0 SADEN 7 0 Slave 0 address mask This byte is a mask byte of UART0 that contains don t care bits defined b...

Page 90: ...Value SADEN_1 BAH all pages 0000_0000 b 7 6 5 4 3 2 1 0 SADEN_1 7 0 R W Bit Name Description 7 0 SADEN_1 7 0 Slave 1 address mask This byte is a mask byte of UART1 that contains don t care bits defin...

Page 91: ...NUAL SADDR_1 Slave 1 Address Regiser Address Reset Value SADDR_1 BBH all pages 0000_0000 b 7 6 5 4 3 2 1 0 SADDR_1 7 0 R W Bit Name Description 7 0 SADDR_1 7 0 Slave 1 address This byte specifies the...

Page 92: ...e I 2 C data to be transmitted or a byte which has just received Data in I2DAT remains as long as SI is logic 1 The result of reading or writing I2DAT during I 2 C transceiving progress is unpredicted...

Page 93: ...7 3 I2STAT 7 3 I 2 C status code The MSB five bits of I2STAT contains the status code There are 27 possible status codes When I2STAT is F8H no relevant state information is available and SI flag keep...

Page 94: ...register determines the clock rate of I 2 C bus when the device is in a master mode The clock rate follows the equation 1 CLK 2 I 4 FSYS The default value will make the clock rate of I 2 C bus 400k bp...

Page 95: ...W R W R W Bit Name Description 2 I2TOCEN I 2 C time out counter enable 0 I 2 C time out counter Disabled 1 I 2 C time out counter Enabled 1 DIV I 2 C time out counter clock divider 0 The clock of I 2...

Page 96: ...After SI is set the software should read I2STAT register to determine which step has been passed and take actions for next step SI is cleared by software Before the SI is cleared the low period of I2...

Page 97: ...IES TECHNICAL REFERENCE MANUAL Bit Name Description 0 I2CPX I2C pins select 0 Assign I2C0_SCL to P1 3 and I2C0_SDA to P1 4 1 Assign I2C0_SCL to P0 2 and I2C0_SDA to P1 6 Note that I2C pins will exchan...

Page 98: ...d address I 2 C device by sending the same address in the first byte data after a START or a repeated START condition If the AA flag is set this I 2 C device will acknowledge the master after receivin...

Page 99: ...NICAL REFERENCE MANUAL ADCRL ADC Result Low Byte Regiser Address Reset Value ADCRL C2H page 0 0000_0000b 7 6 5 4 3 2 1 0 ADCR 3 0 R Bit Name Description 3 0 ADCR 3 0 ADC result low byte The least sign...

Page 100: ...ICAL REFERENCE MANUAL ADCRH ADC Result High Byte Regiser Address Reset Value ADCRH C3H page 0 0000_0000b 7 6 5 4 3 2 1 0 ADCR 11 4 R Bit Name Description 7 0 ADCR 11 4 ADC result high byte The most si...

Page 101: ...erial port 0 baud rate clock source This bit selects which Timer is used as the baud rate clock source when serial port 0 is in Mode 1 or 3 0 Timer 1 1 Timer 3 4 TF3 Timer 3 overflow flag This bit is...

Page 102: ...IES TECHNICAL REFERENCE MANUAL RL3 Timer 3 Reload Low Byte Regiser Address Reset Value RL3 C5H Page 0 0000_0000b 7 6 5 4 3 2 1 0 RL3 7 0 R W Bit Name Description 7 0 RL3 7 0 Timer 3 reload low byte It...

Page 103: ...ES TECHNICAL REFERENCE MANUAL RH3 Timer 3 Reload High Byte Regiser Address Reset Value RL3 C6H Page 0 0000_0000b 7 6 5 4 3 2 1 0 RH3 7 0 R W Bit Name Description 7 0 RH3 7 0 Timer 3 reload high byte I...

Page 104: ...PWM0_CH5 pin functions as P1 5 1 P1 5 PWM0_CH5 pin functions as PWM0 channel 5 output 3 PIO13 P0 4 PWM3 pin function select 0 P0 4 PWM0_CH3 pin functions as P0 4 1 P0 4 PWM0_CH3 pin functions as PWM0...

Page 105: ...0 TA 7 0 W Bit Name Description 7 0 TA 7 0 Timed access The timed access register controls the access to protected SFRs To access protected bits user should first write AAH to the TA and immediately f...

Page 106: ...h occurs If the Timer 2 interrupt and the global interrupt are enable setting this bit will make CPU execute Timer 2 interrupt service routine This bit is not automatically cleared via hardware and sh...

Page 107: ...R Capture auto clear This bit is valid only under Timer 2 auto reload mode It enables hardware auto clearing TH2 and TL2 counter registers after they have been transferred in to RCMP2H and RCMP2L whil...

Page 108: ...Regiser Address Reset Value RCMP2L CAH all pages 0000_0000b 7 6 5 4 3 2 1 0 RCMP2L 7 0 R W Bit Name Description 7 0 RCMP2L 7 0 Timer 2 reload compare low byte This register stores the low byte of comp...

Page 109: ...egiser Address Reset Value RCMP2H CBH all pages 0000_0000b 7 6 5 4 3 2 1 0 RCMP2H 7 0 R W Bit Name Description 7 0 RCMP2H 7 0 Timer 2 reload compare high byte This register stores the high byte of com...

Page 110: ...CHNICAL REFERENCE MANUAL TL2 Timer 2 Low Byte Regiser Address Reset Value TL2 CCH all pages 0000_0000b 7 6 5 4 3 2 1 0 TL2 7 0 R W Bit Name Description 7 0 TL2 7 0 Timer 2 low byte The TL2 register is...

Page 111: ...CHNICAL REFERENCE MANUAL TH2 Timer 2 High Byte Regiser Address Reset Value TH2 CDH Page 0 0000_0000b 7 6 5 4 3 2 1 0 TH2 7 0 R W Bit Name Description 7 0 TH2 7 0 Timer 2 high byte The TH2 register is...

Page 112: ...EFERENCE MANUAL ADCMPL ADC Compare Low Byte Regiser Address Reset Value ADCMPL CEH page 0 0000_0000b 7 6 5 4 3 2 1 0 ADCMP 3 0 W R Bit Name Description 3 0 ADCMP 3 0 ADC compare low byte The least sig...

Page 113: ...FERENCE MANUAL ADCMPH ADC Compare High Byte Regiser Address Reset Value ADCMPH CFH page 0 0000_0000b 7 6 5 4 3 2 1 0 ADCMP 11 4 W R Bit Name Description 7 0 ADCMP 11 4 ADC compare high byte The most s...

Page 114: ...which R0 to R7 locate RS1 RS0 Register Bank RAM Address 0 0 0 00H to 07H 0 1 1 08H to 0FH 1 0 2 10H to 17H 1 1 3 18H to 1FH 3 RS0 2 V Overflow flag OV is used for a signed character operands For a AD...

Page 115: ...AL REFERENCE MANUAL PWMPH PWM Period High Byte Regiser Address Reset Value PWMPH D1H all pages 0000_0000b 7 6 5 4 3 2 1 0 PWMP 15 8 R W Bit Name Description 7 0 PWMP 15 8 PWM period high byte This byt...

Page 116: ...l pages 0000 _0000 b PWM1H D3H all pages 0000 _0000 b PWM2H D4H all pages 0000 _0000 b PWM3H D5H all pages 0000 _0000 b PWM4H C4H page 1 0000 _0000 b PWM5H C5H page 1 0000 _0000 b 7 6 5 4 3 2 1 0 PWM0...

Page 117: ...tive Polarity Regiser Address Reset Value PNP D6H all pages 0000_0000b 7 6 5 4 3 2 1 0 PNP5 PNP4 PNP3 PNP2 PNP1 PNP0 R W R W R W R W R W R W Bit Name Description n PNPn PWMn negative polarity output e...

Page 118: ...BF Fault Brake flag This flag is set when FBINEN is set as 1 and FB pin detects an edge which matches FBINLS FBD 6 selection This bit is cleared by software After FBF is cleared Fault Brake data outpu...

Page 119: ...ill be automatically cleared via hardware The meaning of writing and reading LOAD bit is different Writing 0 No effect 1 Load new period and duty in their buffers while a PWM period is completed Readi...

Page 120: ...ICAL REFERENCE MANUAL PWMPL PWM Period Low Byte Regiser Address Reset Value PWMPL D9H all pages 0000_0000b 7 6 5 4 3 2 1 0 PWMP 7 0 R W Bit Name Description 7 0 PWMP 7 0 PWM period low byte This byte...

Page 121: ...ges 0000 _0000 b PWM1L DBH all pages 0000 _0000 b PWM2L DCH all pages 0000 _0000 b PWM3L DDH all pages 0000 _0000 b PWM4L CCH Page 1 0000 _0000 b PWM5L CCH Page 1 0000 _0000 b 7 6 5 4 3 2 1 0 PWM0 7 0...

Page 122: ...pin function select 0 P0 1 PWM0_CH4 pin functions as P0 1 1 P0 1 PWM0_CH4 pin functions as PWM4 output 3 PIO03 P0 0 PWM0 channel 3 pin function select 0 P0 0 PWM0_CH3 pin functions as P0 0 1 P0 0 PWM...

Page 123: ...R W R W R W R W Bit Name Description 5 GP Group mode enable This bit enables the group mode If enabled the duty of first three pairs of PWM are decided by PWM01H and PWM01L rather than their original...

Page 124: ...tor Regiser Address Reset Value ACC E0H all pages Bit addressable 0000_0000b 7 6 5 4 3 2 1 0 ACC 7 ACC 6 ACC 5 ACC 4 ACC 3 ACC 2 ACC 1 ACC 0 R W R W R W R W R W R W R W R W Bit Name Description 7 0 AC...

Page 125: ...elect When ADCEX ADCCON1 1 is set these bits select which condition triggers ADC conversion 00 Falling edge on PWM0 2 4 or STADC pin 01 Rising edge on PWM0 2 4 or STADC pin 10 Central point of a PWM p...

Page 126: ...alue defined ADCF will be set to 1 This condition base on ADCMPH ADCMPL and ADCMPOP register define The ADCF register changes to 1 only when ADC comparing result matches the condition and then enters...

Page 127: ...0 ADC external trigger delay counter low byte This 8 bit field combined with ADCCON2 0 forms a 9 bit counter This counter inserts a delay after detecting the external trigger An A D converting starts...

Page 128: ...w Byte Regiser Address Reset Value C0L E4H all pages 0000_0000b C1L E6H all pages 0000_0000b C2L EDH all pages 0000_0000b 7 6 5 4 3 2 1 0 C0L 7 0 R W Bit Name Description 7 0 CnL 7 0 Input capture n r...

Page 129: ...h Byte Regiser Address Reset Value C0H E4H all pages 0000_0000b C1H E7H all pages 0000_0000b C2H EEH all pages 0000_0000b 7 6 5 4 3 2 1 0 C0H 7 0 R W Bit Name Description 7 0 CnH 7 0 Input capture n r...

Page 130: ...nversion This bit remains logic 1 during A D converting time and is automatically cleared via hardware right after conversion complete The meaning of writing and reading ADCS bit is different Writing...

Page 131: ...triggered 1 Edge triggered 5 PIT3 Pin interrupt channel 3 type select This bit selects which type that pin interrupt channel 3 is triggered 0 Level triggered 1 Edge triggered 4 PIT2 Pin interrupt chan...

Page 132: ...INEN7 PINEN6 PINEN5 PINEN4 PINEN3 PINEN2 PINEN1 PINEN0 R W R W R W R W R W R W R W R W Bit Name Description n PINENn Pin interrupt channel n negative polarity enable This bit enables low level falling...

Page 133: ...IPEN7 PIPEN6 PIPEN5 PIPEN4 PIPEN3 PIPEN2 PIPEN1 PIPEN0 R W R W R W R W R W R W R W R W Bit Name Description n PIPENn Pin interrupt channel n positive polarity enable This bit enables high level rising...

Page 134: ...level R W edge R level R W edge R level R W edge R level R W edge R level R W edge Bit Name Description n PIFn Pin interrupt channel n flag If the edge trigger is selected this flag will be set by ha...

Page 135: ...rupt priority low bit 6 PSPI SPI interrupt priority low bit 5 PFB Fault Brake interrupt priority low bit 4 PWDT WDT interrupt priority low bit 3 PPWM PWM interrupt priority low bit 2 PCAP Input captur...

Page 136: ...ser Address Reset Value B F0H all pages bit addressable 0000_0000b 7 6 5 4 3 2 1 0 B 7 B 6 B 5 B 4 B 3 B 2 B 1 B 0 R W R W R W R W R W R W R W R W Bit Name Description 7 0 B 7 0 B register The B regis...

Page 137: ...R W R W R W R W R W R W R W Bit Name Description 7 4 CAP1 3 0 Input capture channel 0 input pin select 0000 P1 2 IC0 0001 P1 1 IC1 0010 P1 0 IC2 0011 P0 0 IC3 0100 P0 4 IC3 0101 P0 1 IC4 0110 P0 3 IC...

Page 138: ...dress Reset Value CAPCON4 F2H all pages 0000_0000b 7 6 5 4 3 2 1 0 CAP23 CAP22 CAP21 CAP20 R W R W R W R W Bit Name Description 3 0 CAP2 3 0 Input capture channel 0 input pin select 0000 P1 2 IC0 0001...

Page 139: ...s 0 The SPI is configured as Slave mode 1 The SPI is configured as Master mode 3 CPOL SPI clock polarity select CPOL bit determines the idle state level of the SPI clock See Figure 6 9 4 SPI Clock For...

Page 140: ...3 2 1 0 SPIS1 SPIS0 R W R W Bit Name Description 7 2 Reserved 0 SPIS 1 0 SPI Interval time selection between adjacent bytes SPIS 1 0 and CPHA select eight grades of SPI interval time selection betwee...

Page 141: ...overrun event occurs this bit will be set If ESPI and EA are enabled an SPI interrupt will be required This bit should be cleared via software 4 MODF Mode Fault error flag This bit indicates a Mode F...

Page 142: ...0b 7 6 5 4 3 2 1 0 SPDR 7 0 R W Bit Name Description 7 0 SPDR 7 0 Serial peripheral data This byte is used for transmitting or receiving data on SPI bus A write of this byte is a write to the shift re...

Page 143: ...ddress Reset Value AINDIDS F6H all page 0000_0000b 7 6 5 4 3 2 1 0 P11DIDS P03DIDS P04DIDS P05DIDS P06DIDS P07DIDS P30DIDS P17DIDS R W R W R W R W R W R W R W R W Bit Name Description n PnDIDS ADC Cha...

Page 144: ...rupt priority high bit 6 PSPIH SPI interrupt priority high bit 5 PFBH Fault Brake interrupt priority high bit 4 PWDTH WDT interrupt priority high bit 3 PPWMH PWM interrupt priority high bit 2 PCAPH In...

Page 145: ...cast address 4 REN_1 Receiving enable 0 Serial port 1 reception Disabled 1 Serial port 1 reception Enabled in Mode 1 2 or 3 In Mode 0 reception is initiated by the condition REN_1 1 and RI_1 0 3 TB8_1...

Page 146: ...d only when PWM4 5 is under complementary mode 0 No delay on GP4 GP5 pair signals 1 Insert dead time delay on the rising edge of GP4 GP5 pair signals 1 PDT23EN PWM2 3 pair dead time insertion enable T...

Page 147: ...7 6 5 4 3 2 1 0 PDTCNT 7 0 R W Bit Name Description 7 0 PDTCNT 7 0 PWM dead time counter low byte This 8 bit field combined with PDTEN 4 forms a 9 bit PWM dead time counter PDTCNT This counter is vali...

Page 148: ...L PMEN PWM Mask Enable Regiser Address Reset Value PMEN FBH all page 0000_0000b 7 6 5 4 3 2 1 0 PMEN5 PMEN4 PMEN3 PMEN2 PMEN1 PMEN0 R W R W R W R W R W R W Bit Name Description n PMENn PWMn mask enabl...

Page 149: ...Regiser Address Reset Value PMD FCH all page 0000_0000b 7 6 5 4 3 2 1 0 PMD5 PMD4 PMD3 PMD2 PMD1 PMD0 R W R W R W R W R W R W Bit Name Description n PMDn PWMn mask data The PWMn signal outputs mask d...

Page 150: ...L PORDIS POR disable TA protected Regiser Address Reset Value PORDIS FDH all page TA protected 0000_0000b 7 6 5 4 3 2 1 0 PORDIS 7 0 W Bit Name Description 7 0 PORDIS 7 0 POR disable To first writing...

Page 151: ...4 3 2 1 0 PWKT PT3 PS_1 R W R W R W Bit Name Description 2 PWKT WKT interrupt priority low bit 1 PT3 Timer 3 interrupt priority low bit 0 PS_1 Serial port 1 interrupt priority low bit Note EIP1 is us...

Page 152: ...4 3 2 1 0 PWKTH PT3H PSH_1 R W R W R W Bit Name Description 2 PWKTH WKT interrupt priority high bit 1 PT3H Timer 3 interrupt priority high bit 0 PSH_1 Serial port 1 interrupt priority high bit Note EI...

Page 153: ...peed internal oscillator low speed internal oscillator and external clock input Each of them can be the system clock source in the MS51 Different active system clock sources also affect multi function...

Page 154: ...w to ensure a complete clock source switching User can enable the target clock source by writing proper value into CKEN register wait for the clock source stable by polling its status bit in CKSWT reg...

Page 155: ...stable or disabled 1 High speed internal oscillator is enabled and stable 4 Reserved 3 ECLKST External clock input status 0 External clock input is not stable or disabled 1 External clock input is ena...

Page 156: ...revious system clock source switch was successful 1 User tried to switch to an instable or disabled clock source at the previous system clock source switch If switching to an instable clock source thi...

Page 157: ...r Regiser Address Reset Value CKDIV 95H all pages 0000_0000b 7 6 5 4 3 2 1 0 CKDIV 7 0 R W Bit Name Description 7 0 CKDIV 7 0 Clock divider The system clock frequency FSYS follows the equation below a...

Page 158: ...have an external pull up or pull low or enable its internal pull up by setting P20UP P2S 7 Idle Mode 6 2 2 1 Idle mode suspends CPU processing by holding the Program Counter No program code are fetche...

Page 159: ...interrupt service routine ISR for the corresponding external interrupt After the ISR is completed the program execution returns to the instruction after the one which puts the device into Power down...

Page 160: ...d oscillator will start and then program code will execute from 0000H At the same time a power on flag POF PCON 4 will be set 1 to indicate a cold reset a power on process complete Note that the conte...

Page 161: ...e the device is in reset condition it will remain as long as nRESET pin is low After the nRESET high is removed the MCU will exit the reset state and begin code executing from address 0000H If an exte...

Page 162: ...I EIE1 4 0 MCU will reset and this bit will be set via hardware It is recommended that the flag be cleared via software Note If MCU run in OCD debug mode and OCDEN 0 Hard fault reset will disable Only...

Page 163: ...hole system just similar to an external reset initializing the MCU as it reset state The software reset is quite useful in the end of an ISP progress For example if an ISP of Boot Code updating User C...

Page 164: ...in U100_0000b Others UUU0_0000b 7 6 5 4 3 2 1 0 SWRF RSTPINF HardF SLOW GF2 UART0PX 0 DPS R W R W R W R W R W R W R R W Bit Name Description 7 SWRF Software reset flag When the MCU is reset via softwa...

Page 165: ...W R W R W R W Bit Name Description 1 BS Boot select This bit defines from which block that MCU re boots after all resets 0 MCU will re boot from APROM after all resets 1 MCU will re boot from LDROM af...

Page 166: ...apture interrupt 0063H 12 Timer 1 overflow 001BH 3 PWM interrupt 006BH 13 Serial port 0 interrupt 0023H 4 Fault Brake interrupt 0073H 14 Timer 2 event 002BH 5 Serial port 1 interrupt 007BH 15 I 2 C st...

Page 167: ...ked only if no other interrupt is already executing Again the low priority interrupt cannot preempt another low priority interrupt even if the later one is higher in natural priority 4 If two interrup...

Page 168: ...The conditions for generating the LCALL are 1 An interrupt of equal or higher priority is not currently being serviced 2 The current polling cycle is the last cycle of the instruction currently being...

Page 169: ...16 clock cycles This period includes 5 clock cycles to complete RETI 6 clock cycles to complete the longest instruction 1 clock cycle to detect the interrupt and 4 clock cycles to complete the hardwa...

Page 170: ...ADC interrupt Disabled 1 Interrupt generated by ADCF ADCCON0 7 Enabled 5 EBOD Enable brown out interrupt 0 Brown out detection interrupt Disabled 1 Interrupt generated by BOF BODCON0 3 Enabled 4 ES En...

Page 171: ...PSR 4 Enable 5 EFB Enable Fault Brake interrupt 0 Fault Brake interrupt Disabled 1 Interrupt generated by FBF FBD 7 Enabled 4 EWDT Enable WDT interrupt 0 WDT interrupt Disabled 1 Interrupt generated b...

Page 172: ...EWKT ET3 ES_1 R W R W R W Bit Name Description 2 EWKT Enable WKT interrupt 0 WKT interrupt Disabled 1 Interrupt generated by WKTF WKCON 4 Enabled 1 ET3 Enable Timer 3 interrupt 0 Timer 3 interrupt Di...

Page 173: ...terrupt priority low bit 5 PBOD Brown out detection interrupt priority low bit 4 PS Serial port 0 interrupt priority low bit 3 PT1 Timer 1 interrupt priority low bit 2 PX1 External interrupt 1 priorit...

Page 174: ...y high bit 5 PBOD Brown out detection interrupt priority high bit 4 PSH Serial port 0 interrupt priority high bit 3 PT1H Timer 1 interrupt priority high bit 2 PX1H External interrupt 1 priority high b...

Page 175: ...rupt priority low bit 6 PSPI SPI interrupt priority low bit 5 PFB Fault Brake interrupt priority low bit 4 PWDT WDT interrupt priority low bit 3 PPWM PWM interrupt priority low bit 2 PCAP Input captur...

Page 176: ...rupt priority high bit 6 PSPIH SPI interrupt priority high bit 5 PFBH Fault Brake interrupt priority high bit 4 PWDTH WDT interrupt priority high bit 3 PPWMH PWM interrupt priority high bit 2 PCAPH In...

Page 177: ...4 3 2 1 0 PWKT PT3 PS_1 R W R W R W Bit Name Description 2 PWKT WKT interrupt priority low bit 1 PT3 Timer 3 interrupt priority low bit 0 PS_1 Serial port 1 interrupt priority low bit Note EIP1 is us...

Page 178: ...4 3 2 1 0 PWKTH PT3H PSH_1 R W R W R W Bit Name Description 2 PWKTH WKT interrupt priority high bit 1 PT3H Timer 3 interrupt priority high bit 0 PSH_1 Serial port 1 interrupt priority high bit Note EI...

Page 179: ...er this flag follows the inverse of the INT1 input signal s logic level Software cannot control it 2 IT1 External interrupt 1 type select This bit selects by which type that INT1 is triggered 0 INT1 i...

Page 180: ...23 5 s After IAP action completed the Program Counter continues to run the following instructions The IAPGO bit will be automatically cleared An IAP failure flag IAPFF CHPCON 6 can be check whether t...

Page 181: ...cide whether IAP erasing or programming is inhibited by brown out status This bit is valid only when brown out detection is enabled 1 IAP erasing or programming is inhibited if VDD is lower than VBOD...

Page 182: ...y 1 CPU memory address 0xff80 0xffff is mapping to SPROM memory 3 SPUEN SPROM Memory space updated enable TA protected 0 Inhibit erasing or programming SPROM bytes by IAP 1 Allow erasing or programmin...

Page 183: ...es 0000_0000b 7 6 5 4 3 2 1 0 IAPA 7 0 R W Bit Name Description 7 0 IAPA 7 0 IAP address low byte IAPAL contains address IAPA 7 0 for IAP operations IAPFD IAP Flash Data Regiser Address Reset Value IA...

Page 184: ...es the HIRC running If the external clock source is selected disabling IAP will stop the HIRC for saving power consumption Note that a write to IAPEN is TA protected 2 When the LOCK bit CONFIG0 1 is a...

Page 185: ...00000001b write 1 to IAPGO to trigger IAP process MOV IAPCN BYTE_PROGRAM_AP Program 201h with 55h MOV IAPAH 02h MOV IAPAL 01h MOV IAPFD 55h MOV TA 0Aah MOV TA 55h ORL IAPTRG 00000001b MOV TA 0Aah MOV...

Page 186: ...sh Memory supports both hardware programming and In Application Programming IAP If the product is just under development or the end product needs firmware updating in the hand of an end user the hardw...

Page 187: ...QU 11100001b BYTE_READ_CONFIG EQU 11000000b ORG 0000h CLR EA disable all interrupts CALL Enable_IAP CALL Enable_AP_Update CALL Erase_AP erase AP data CALL Program_AP programming AP data CALL Disable_A...

Page 188: ...CONFIG update RET Disable_CONFIG_Update MOV TA 0Aah MOV TA 55h ANL IAPUEN 11111011b CFUEN 0 disable CONFIG update RET Trigger_IAP MOV TA 0Aah IAPTRG is TA protected MOV TA 55h ORL IAPTRG 00000001b wr...

Page 189: ...ogram_AP_Verify_Error INC DPTR INC IAPAL MOV A IAPAL CJNE A 14 Program_AP_Verify_Loop RET Program_AP_Verify_Error CALL Disable_IAP MOV P0 00h SJMP IAP CONFIG Function Erase_CONFIG MOV IAPCN ALL_ERASE_...

Page 190: ...omized firmware There are three signal pins nRESET ICPDA and ICPCK involved in ICP function nRESET is used to enter or exit ICP mode ICPDA is the data input and output pin ICPCK is the clock input pin...

Page 191: ...d for OCD mode selection 2 The OCDDA pin is physically located on the same pin P5 0 Therefore neither its I O function nor shared multi functions can be emulated 3 The OCDCK pin is physically located...

Page 192: ...h MS51 chip was factory pre programmed with a 96 bit width serial number which is guaranteed to be unique The serial number is called Unique Code The user can read the Unique Code only by IAP command...

Page 193: ...ch suppression capability All I O pins also have bit controllable slew rate select ability via software The control registers are PxSR By default the slew rate is slow If user would like to increase t...

Page 194: ...utput driving Port Pin Input Port Latch P N VDD Strong Figure 6 4 2 Push Pull Mode Structure Input Only Mode 6 4 1 3 Input only mode provides true high impedance input path Although a quasi bidirectio...

Page 195: ...gisters of GPIO The MS51 has a lot of I O control registers to provide flexibility in all kinds of applications The SFR related with I O ports can be categorized into four groups input and output cont...

Page 196: ...l 6 4 2 2 These registers control GPIO mode which is configurable among four modes input only quasi bidirectional push pull or open drain Each pin can be configured individually As default after reset...

Page 197: ...ess Reset Value P0S B1H Page 1 0000_0000 b P1S 83H Page 1 0000_0000 b P3S ACH Page 1 0000_0000 b 7 6 5 4 3 2 1 0 PnS 7 PnS 6 PnS 5 PnS 4 PnS 3 PnS 2 PnS 1 PnS 0 R W R W R W R W R W R W R W R W Bit Nam...

Page 198: ...SR Port n Slew Rate Control Register SFR Address Reset Value P0SR 82H Page 1 0000_0000 b P1SR 84H Page 1 0000_0000 b P3SR ADH Page 1 0000_0000 b 7 6 5 4 3 2 1 0 PnSR 7 PnSR 6 PnSR 5 PnSR 4 PnSR 3 PnSR...

Page 199: ...evel triggering event Pin interrupt may be used to wake the CPU up from Idle or Power down mode Each channel of pin interrupt can be enabled and polarity controlled independently by PIPEN and PINEN re...

Page 200: ...ace Block Diagram Pin interrupt is generally used to detect an edge transient from peripheral devices like keyboard or keypad During idle state the system prefers to enter Power down mode to minimize...

Page 201: ...triggered 1 Edge triggered 5 PIT3 Pin interrupt channel 3 type select This bit selects which type that pin interrupt channel 3 is triggered 0 Level triggered 1 Edge triggered 4 PIT2 Pin interrupt chan...

Page 202: ...INEN7 PINEN6 PINEN5 PINEN4 PINEN3 PINEN2 PINEN1 PINEN0 R W R W R W R W R W R W R W R W Bit Name Description n PINENn Pin interrupt channel n negative polarity enable This bit enables low level falling...

Page 203: ...IPEN7 PIPEN6 PIPEN5 PIPEN4 PIPEN3 PIPEN2 PIPEN1 PIPEN0 R W R W R W R W R W R W R W R W Bit Name Description n PIPENn Pin interrupt channel n positive polarity enable This bit enables high level rising...

Page 204: ...level R W edge R level R W edge R level R W edge R level R W edge R level R W edge Bit Name Description n PIFn Pin interrupt channel n flag If the edge trigger is selected this flag will be set by ha...

Page 205: ...never a timer overflow occurs The same device pins that are used for the T0 and T1 count inputs are also used for the timer toggle outputs This function is enabled by control bits T0OE and T1OE in the...

Page 206: ...ftware intervention Note that only Timer1 can be the baud rate source for UART Counting is enabled by setting the TR0 TR1 bit as 1 and proper setting of GATE and INT0 INT1 pins The functions of GATE a...

Page 207: ...logic level 1 Timer 1 will clock only when TR1 is 1 and INT1 is logic 1 6 C T Timer 1 Counter Timer select 0 Timer 1 is incremented by internal system clock 1 Timer 1 is incremented by the falling edg...

Page 208: ...be preserved in TH0 and TL0 1 Timer 0 Enabled 3 IE1 External interrupt 1 edge flag If IT1 1 falling edge trigger this flag will be set by hardware when a falling edge is detected It remain set until c...

Page 209: ...0 high byte The TH0 register is the high byte of the 16 bit counting register of Timer 0 TL1 Timer 1 Low Byte Regiser Address Reset Value TL1 8BH all pages 0000_0000b 7 6 5 4 3 2 1 0 TL1 7 0 R W Bit...

Page 210: ...patibility 1 The clock source of Timer 0 is direct the system clock 2 T0OE Timer 0 output enable 0 Timer 0 output Disabled 1 Timer 0 output Enabled from T0 pin Note that Timer 0 output should be enabl...

Page 211: ...errupt CAPF0 CAPF1 CAPF2 CMPCR T2MOD 2 Clear Timer 2 CAP0 CAP1 CAP2 TH2 TL2 Clear Counter CAPF0 0000 0001 0010 0011 0100 0101 0110 0111 P1 5 IC7 P0 5 IC6 P0 3 IC5 P0 1 IC4 P0 0 IC3 P1 0 IC2 P1 1 IC1 P...

Page 212: ...re the unique Timer 2 Each trigger edge detector is selected individually by setting corresponding bits in CAPCON1 It supports positive edge capture negative edge capture or any edge capture Each inpu...

Page 213: ...RCMP2L TH2 TL2 TR2 T2CON 2 Timer 2 Module CMPCR T2MOD 2 Clear Timer 2 C0H C0L Noise Filter ENF0 CAPCON2 4 or 00 01 10 CAP0LS 1 0 CAPCON1 1 0 CAPEN0 CAPCON0 4 CAPF0 Input Capture 0 Module Input Captur...

Page 214: ...the Timer 2 interrupt and the global interrupt are enable setting this bit will make CPU execute Timer 2 interrupt service routine This bit is not automatically cleared via hardware and should be clea...

Page 215: ...R Capture auto clear This bit is valid only under Timer 2 auto reload mode It enables hardware auto clearing TH2 and TL2 counter registers after they have been transferred in to RCMP2H and RCMP2L whil...

Page 216: ...he low byte of compare value when Timer 2 is configured in compare mode Also it holds the low byte of the reload value in auto reload mode RCMP2H Timer 2 Reload Compare High Byte Regiser Address Reset...

Page 217: ...CHNICAL REFERENCE MANUAL TL2 Timer 2 Low Byte Regiser Address Reset Value TL2 CCH all pages 0000_0000b 7 6 5 4 3 2 1 0 TL2 7 0 R W Bit Name Description 7 0 TL2 7 0 Timer 2 low byte The TL2 register is...

Page 218: ...0 R W Bit Name Description 7 0 TH2 7 0 Timer 2 high byte The TH2 register is the high byte of the 16 bit counting register of Timer 2 Note that the TH2 and TL2 are accessed separately It is strongly r...

Page 219: ...nable 0 Input capture channel 1 Disabled 1 Input capture channel 1 Enabled 4 CAPEN0 Input capture 0 enable 0 Input capture channel 0 Disabled 1 Input capture channel 0 Enabled 3 Reserved 2 CAPF2 Input...

Page 220: ...P0LS 1 0 R W R W R W Bit Name Description 7 6 Reserved 5 4 CAP2LS 1 0 Input capture 2 level select 00 Falling edge 01 Rising edge 10 Either rising or falling edge 11 Reserved 3 2 CAP1LS 1 0 Input capt...

Page 221: ...6 ENF2 Enable noise filer on input capture 2 0 Noise filter on input capture channel 2 Disabled 1 Noise filter on input capture channel 2 Enabled 5 ENF1 Enable noise filer on input capture 1 0 Noise f...

Page 222: ...w Byte Regiser Address Reset Value C0L E4H all pages 0000_0000b C1L E6H all pages 0000_0000b C2L EDH all pages 0000_0000b 7 6 5 4 3 2 1 0 C0L 7 0 R W Bit Name Description 7 0 CnL 7 0 Input capture n r...

Page 223: ...h Byte Regiser Address Reset Value C0H E4H all pages 0000_0000b C1H E7H all pages 0000_0000b C2H EEH all pages 0000_0000b 7 6 5 4 3 2 1 0 C0H 7 0 R W Bit Name Description 7 0 CnH 7 0 Input capture n r...

Page 224: ...R W R W R W R W R W R W R W Bit Name Description 7 4 CAP1 3 0 Input capture channel 1 input pin select 0000 P1 2 IC0 0001 P1 1 IC1 0010 P1 0 IC2 0011 P0 0 IC3 0100 P0 4 IC3 0101 P0 1 IC4 0110 P0 3 IC...

Page 225: ...PS 2 0 T3CON 2 0 and fill the reload value into RH3 and RL3 registers to determine its overflow rate User then can set TR3 T3CON 3 to start counting When the counter rolls over FFFFH TF3 T3CON 4 is se...

Page 226: ...ically cleared by hardware when the program executes the Timer 3 interrupt service routine This bit can be set or cleared by software 3 TR3 Timer 3 run control 0 Timer 3 is halted 1 Timer 3 starts run...

Page 227: ...b 7 6 5 4 3 2 1 0 RL3 7 0 R W Bit Name Description 7 0 RL3 7 0 Timer 3 reload low byte It holds the low byte of the reload value of Timer 3 RH3 Timer 3 Reload High Byte Regiser Address Reset Value RL3...

Page 228: ...e out reset timer and it stops running during Idle or Power down mode Others WDT is Enabled as a time out reset timer and it keeps running during Idle or Power down mode The WDT is implemented with a...

Page 229: ...eared for user monitoring it Once a reset due to WDT occurs the WDT reset flag WDTRF WDCON 3 will be set This bit keeps unchanged after any reset other than a power on reset User may clear WDTRF via s...

Page 230: ...nothing needs to be served to save power consumption After a while the CPU will be woken up to check if anything needs to be served at an interval of programmed period implemented by Timer 0 3 Howeve...

Page 231: ...T counter is not yet cleared 5 WDTF WDT time out flag This bit indicates an overflow of WDT counter This flag should be cleared by software 4 WIDPD WDT running in Idle or Power down mode This bit is v...

Page 232: ...t automatically enabled along with WKT configuration User should manually enable the selected clock source and waiting for stability to ensure a proper operation The WKT is implemented simply as a 8 b...

Page 233: ...global interrupt are enabled setting this bit will make CPU execute WKT interrupt service routine This bit is not automatically cleared via hardware and should be cleared via software 3 WKTR WKT run...

Page 234: ...Self Wake up Timer Reload Byte Regiser Address Reset Value RWK 86H all pages 0000_0000b 7 6 5 4 3 2 1 0 RWK 7 0 R W Bit Name Description 7 0 RWK 7 0 WKT reload byte It holds the 8 bit reload value of...

Page 235: ...ts through RXD pin TXD outputs the shift clocks 8 bit frame of data are transmitted or received Mode 0 therefore provides half duplex communication because the transmitting or receiving data is via th...

Page 236: ...o 0 transition at RXD Data will be sampled and shifted in at the selected baud rate In the midst of the stop bit certain conditions should be met to load SBUF with the received data 1 RI SCON 0 0 and...

Page 237: ...tions fail there will be no data loaded and RI will remain 0 After above receiving progress the serial control will look forward another 1 to 0 transition on RXD pin to start next data reception Mode...

Page 238: ...1 Time1 TM1 CKCON 3 0 TH1 256 12 F 16 1 SYS Time1 TM1 CKCON 3 1 TH1 256 F 16 1 SYS Timer 3 RL3 RH3 256 65536 scale Pre F 16 1 SYS 2 11 10 0 FSYS divided by 64 1 FSYS divided by 32 3 11 11 0 Time 1 1 T...

Page 239: ...rt 0 UART0 use timer 1 as baudrate generator Formula is TH1 256 F 16 1 SYS SCON 0x50 UART0 Mode1 REN 1 TI 1 TMOD 0x20 Timer1 set to Mode2 auto reload mode must PCON 0x80 UART0 Double Rate Enable CKCON...

Page 240: ...00000 FD FFFD 0 000000 750000 FE FFFE 0 000000 1500000 FF FFFF 0 000000 16MHz 4800 30 FF30 0 160256 9600 98 FF98 0 160256 19200 CC FFCC 0 160256 38400 E6 FFE6 0 160256 57600 EF FFEF 2 124183 115200 F7...

Page 241: ...slaves to UART Mode 2 or 3 2 Write the SM2 bit of all the slave devices to 1 3 The master device s transmission protocol is First byte the address identifying the target slave device 9th bit 1 Next by...

Page 242: ...since slave 1 requires 0 in bit 1 A unique address for slave 1 would be 11000001b since 1 in bit 0 will exclude slave 0 Both slaves can be selected at the same time by an address which has bit 0 0 for...

Page 243: ...W R W Bit Name Description 7 SM0 FE Serial port mode select SMOD0 PCON 6 0 See Table 6 8 1 Serial Port UART0 Mode baudrate Description for details SMOD0 PCON 6 1 SM0 FE bit is used as frame error FE s...

Page 244: ...hardware when a data frame has been transmitted by the serial port 0 after the 8th bit in Mode 0 or the last data bit in other modes When the serial port 0 interrupt is enabled setting this bit cause...

Page 245: ...cast address 4 REN_1 Receiving enable 0 Serial port 1 reception Disabled 1 Serial port 1 reception Enabled in Mode 1 2 or 3 In Mode 0 reception is initiated by the condition REN_1 1 and RI_1 0 3 TB8_1...

Page 246: ...MS51 Dec 17 2019 Page 246 of 316 Rev 1 01 MS51 SERIES TECHNICAL REFERENCE MANUAL...

Page 247: ...W R W RW R W R W R W R W R W Bit Name Description 7 SMOD Serial port 0 double baud rate enable Setting this bit doubles the serial port baud rate when UART0 is in Mode 2 or when Timer 1 overflow is us...

Page 248: ...MOD0_1 BRCK TF3 TR3 T3PS 2 0 R W R W R W R W R W R W Bit Name Description 7 SMOD_1 Serial port 1 double baud rate enable Setting this bit doubles the serial port baud rate when UART1 is in Mode 2 See...

Page 249: ...Name Description 7 0 SBUF 7 0 Serial port 0 data buffer This byte actually consists two separate registers One is the receiving resister and the other is the transmitting buffer When data is moved to...

Page 250: ...Name Description 7 0 SBUF1 7 0 Serial port 1 data buffer This byte actually consists two separate registers One is the receiving resister and the other is the transmitting buffer When data is moved t...

Page 251: ...ES Enable serial port 0 interrupt 0 Serial port 0 interrupt Disabled 1 Interrupt generated by TI SCON 1 or RI SCON 0 Enabled EIE1 Extensive Interrupt Enable 1 Regiser Address Reset Value EIE1 9CH all...

Page 252: ...fies the microcontroller s own slave address for UATR0 multi processor communication SADEN Slave 0 Address Mask Regiser Address Reset Value SADEN B9H all pages 0000_0000 b 7 6 5 4 3 2 1 0 SADEN 7 0 R...

Page 253: ...ifies the microcontroller s own slave address for UART1 multi processor communication SADEN1 Slave 1 Address Mask Regiser Address Reset Value SADEN_1 BAH all pages 0000_0000 b 7 6 5 4 3 2 1 0 SADEN1 7...

Page 254: ...1 0 SWRF RSTPINF HardF SLOW GF2 UART0PX 0 DPS R W R W R W R W R W R W R R W Bit Name Description 2 UART0PX Serial port 0 pin exchange 0 Assign RXD to P0 7 and TXD to P0 6 by default 1 Exchange RXD to...

Page 255: ...SPI Block Diagram Figure15 1 SPI Block Diagram shows SPI block diagram It provides an overview of SPI architecture in this device The main blocks of SPI are the SPI control register logic SPI status l...

Page 256: ...des auto activating function to toggle SS between each byte transfer MISO MOSI SPCLK SS I O PORT 0 1 2 3 I O PORT 0 1 2 3 SO SI SCK SS Slave device 1 Master Slave MCU1 MISO MOSI SPCLK SS Master Slave...

Page 257: ...in from the Slave on the MISO pin After 8 bit data transfer complete SPIF SPInSR 7 will automatically set via hardware to indicate one byte data transfer complete At the same time the data received f...

Page 258: ...executed Concerning the Slave mode the SS signal needs to be taken care As shown in Figure 6 9 4 SPI Clock Formats when CPHA 0 the first SPCLK edge is the sampling strobe of MSB for an example of LSB...

Page 259: ...SPI Clock and Data Format with CPHA 0 Transfer Progress 1 internal signal SPCLK Cycles SPCLK CPOL 0 MOSI SS output of Master 2 SPIF Master 1 2 3 4 5 6 7 8 SPCLK CPOL 1 MSB MISO 6 5 4 3 2 1 LSB MSB Inp...

Page 260: ...rated if ESPI and EA are enabled 6 9 5 Write Collision Error The SPI is signal buffered in the transfer direction and double buffered in the receiving and transmit direction New data for transmission...

Page 261: ...event interrupt requests All of them locate in SPInSR SPIF will be set after completion of data transfer with external device or a new data have been received and copied to SPInDR MODF becomes set to...

Page 262: ...t determines the idle state level of the SPI clock See Figure 6 9 4 SPI Clock Formats 0 The SPI clock is low in idle state 1 The SPI clock is high in idle state 2 CPHA SPI clock phase select CPHA bit...

Page 263: ...if SPIF is set 6 WCOL Write collision error flag This bit indicates a write collision event Once a write collision event occurs this bit will be set It should be cleared via software 5 SPIOVF SPI over...

Page 264: ...R Serial Peripheral Data Register Regiser Address Reset Value SPDR F5H all page 0000_0000b 7 6 5 4 3 2 1 0 SPDR 7 0 R W Bit Name Description 7 0 SPDR 7 0 Serial peripheral data This byte is used for t...

Page 265: ...high In MS51 user should set output latches of I2C0_SCL and I2C0_SDA As logic 1 before enabling the I 2 C function by setting I2CEN SDA SCL Slave Device SDA SCL Other MCU SDA SCL VDD RUP RUP SDA SCL...

Page 266: ...out first generating a STOP condition Various combinations of read write formats are then possible within such a transfer SDA SCL START STOP START Repeated START STOP Figure 6 10 3 START Repeated STAR...

Page 267: ...eceiver mode Note that the address 0x00 is reserved for General Call and cannot be used as a slave address therefore in theory a 7 bit addressing I 2 C bus accepts 127 devices with their slave address...

Page 268: ...2C0_SDA while another master transmits a 0 low switches off its data output stage because the level on the bus does not match its own level The arbitration lost master switches to the not addressed sl...

Page 269: ...the SI flag of I2C_CTL0 register will be set But the SI flag will not be set when I2C STOP If the I2C interrupt control bit INTEN I2C_CTL0 7 is set appropriate action or software branch of the new sta...

Page 270: ...er MT I2CnDAT SLA W I2C_DAT SLA W STA STO SI AA 0 0 1 1 Arbitration Lost ACK STATUS 0x68 0x78 0xB0 ACK To corresponding states in slave mode Figure 6 10 10 Flow and Status of Master Transmitter Mode M...

Page 271: ...iver 6 10 2 3 In the slave receiver mode several bytes of data are received form a master transmitter Before a transmission is commenced I2CnADDRx should be loaded with the address to which the device...

Page 272: ...be recognized Send START when bus free STA STO SI AA 0 0 1 0 Switch to not addressed mode Own SLA will not be recognized Become I2 C Master Become I2 C Master Bus Free S I2CnDAT SLA R ACK STA STO SI A...

Page 273: ...2CnDAT Data STA STO SI AA 0 0 1 0 STATUS 0x90 STATUS 0x98 S STA STO SI AA 1 0 1 1 Switch to not addressed mode Own SLA will be recognized Send START when bus free S STA STO SI AA 1 0 1 0 Switch to not...

Page 274: ...ional clock pulses when the STA bit is set but no START condition can be generated because the I2C0_SDA line is pulled low When the I2C0_SDA line is eventually released a normal START condition is tra...

Page 275: ...as 1 CPU will execute the I 2 C interrupt service routine once any of these two flags is set User needs to check flags to determine what event caused the interrupt Both of I 2 C flags are cleared by s...

Page 276: ...ith previous data bytes until ready for receiving the next byte The serial transaction is suspended until SI is cleared by software After SI is cleared I 2 C bus will continue to generate START or rep...

Page 277: ...always read as 0 I2DAT I 2 C Data Regiser Address Reset Value I2DAT BCH all pages 0000_0000 b 7 6 5 4 3 2 1 0 I2DAT 7 0 R W Bit Name Description 7 0 I2DAT 7 0 I 2 C data I2DAT contains a byte of the...

Page 278: ...l 0 because address 0x00 is reserved for General Call 0 GC General Call bit In master mode This bit has no effect In slave mode 0 The General Call is always ignored 1 The General Call is recognized if...

Page 279: ...Routine The following software example in C language for KEIL TM C51 compiler shows the typical structure of the I 2 C interrupt service routine including the 26 state service routines and may be use...

Page 280: ...er Mode case 0x40 40H SLA R transmitted ACK received AA 1 ACK next received DATA break case 0x48 48H SLA R transmitted NACK received STO 1 AA 1 break case 0x50 50H DATA received ACK transmitted DATA_R...

Page 281: ...r addressing break case 0x90 90H previous General Call DATA received ACK returned DATA_RECEIVED3 I2DAT if To_RX_Last_Data3 AA 0 else AA 1 break case 0x98 98H previous General Call DATA received NACK r...

Page 282: ...l be transmitted AA 0 else AA 1 break case 0Xc0 C0H previous own SLA R DATA transmitted NACK received not addressed SLAVE mode entered AA 1 break case 0Xc8 C8H previous own SLA R last DATA trans mitte...

Page 283: ...lectable from 1 1 1 128 The PWM period is defined by effective 16 bit period registers PWMnPH PWMnPL The period is the same for all PWM channels for they share the same 16 bit period counter The duty...

Page 284: ...YS clear counter PWM1 buffer PWM1 Register PG1 PWM2 buffer PWM2 Register PWM3 buffer PWM3 Register PWM4 buffer PWM4 Register PWM5 buffer PWM5 Register PG2 PG3 PG4 PG5 0 1 0 1 0 1 0 1 GP PWMnCON1 5 PWM...

Page 285: ...zation steps below to start generating the PWM signal output In the first step by setting CLRPWM PWMnCON0 4 it ensures the 16 bit up counter reset for the accuracy of the first duration After initiali...

Page 286: ...d PWMnP 1st PWMnCH01 2nd PWMnCH01 1st PG01 output Load PWMnCH01 2nd Load PWMnP 2nd PWMnCH01 2nd duty valid PWMnP 2nd period valid 12 bit counter Figure 6 11 3 PWM Edge aligned Type Waveform The output...

Page 287: ...abled when PWMMOD 1 0 0 1 In this mode PG0 2 4 output PWM signals the same as the independent mode However PG1 3 5 output the out phase PWM signals of PG0 2 4 correspondingly and ignore PG1 3 5 Duty r...

Page 288: ...n input FB is valid when FBINEN PWMnCON1 3 is set When Fault Brake is asserted PWM signals will be individually overwritten by PWMnFBD corresponding bits PWMRUN PWMnCON0 7 will also be automatically c...

Page 289: ...are The PWM interrupt related with PWM waveform is shown as figure below Reserved PWMF central point INTTYP 1 0 1 0 PWMF end point INTTYP 1 0 1 1 Central point End point PWM channel 0 2 4 pin output S...

Page 290: ...g to 0000H After the counter value is cleared CLRPWM will be automatically cleared via hardware The meaning of writing and reading CLRPWM bit is different Writing 0 No effect 1 Clearing PWM 16 bit cou...

Page 291: ...S T1OE T1M T0M T0OE CLOEN R W R W R W R W R W R W R W Bit Name Description 6 PWMCKS PWM clock source select 0 The clock source of PWM is the system clock FSYS 1 The clock source of PWM is the overflow...

Page 292: ...SFR Address Description Reset Value PWM0H D2H all pages PWM Channel 0 Duty High Byte 0000_0000 b PWM1H D3H all pages PWM Channel 1 Duty High Byte 0000_0000 b PWM2H D4H all pages PWM Channel 2 Duty Hi...

Page 293: ...ut 3 PIO03 P0 0 PWM3 pin function select 0 P0 0 PWM3 pin functions as P0 0 1 P0 0 PWM3 pin functions as PWM3 output 2 PIO02 P1 0 PWM2 pin function select 0 P1 0 PWM2 pin functions as P1 0 1 P1 0 PWM2...

Page 294: ...e of GP4 GP5 pair signals 1 PDT23EN PWM2 3 pair dead time insertion enable This bit is valid only when PWM2 3 is under complementary mode 0 No delay on GP2 GP3 pair signals 1 Insert dead time delay on...

Page 295: ...sponding PMENn is set 0 PWMn signal is masked by 0 1 PWMn signal is masked by 1 FBD PWM Fault Brake Data Regiser Address Reset Value FBD D7H all pages 0000_0000b 7 6 5 4 3 2 1 0 FBF FBINLS FBD5 FBD4 F...

Page 296: ...R W R W R W R W Bit Name Description 5 4 INTTYP 1 0 PWM interrupt type select These bit select PWM interrupt type 00 Falling edge on PWMn channel 0 1 2 3 4 5 pin 01 Rising edge on PWMn channel 0 1 2 3...

Page 297: ...nverter The converter then generates a digital result of this analog level via successive approximation and stores the result in the result registers The ADC controller also supports DMA direct memory...

Page 298: ...ly set ADCF ADCCON0 7 and generate an interrupt if enabled The new conversion result will also be stored in ADCRH most significant 8 bits and ADCRL least significant 4 bits The 12 bit ADC result value...

Page 299: ...fter enabling the result compare function the ADCF register changes to 1 only when ADC comparing result matches the condition and then enters interrupt vector if ADC interrupt is enabled After this bi...

Page 300: ...ETGSEL1 ETGSEL0 ADCHS3 ADCHS2 ADCHS1 ADCHS0 R W R W R W R W R W R W R W R W Bit Name Description 7 ADCF ADC flag This flag is set when an A D conversion is completed The ADC result can be read While t...

Page 301: ...C clock source FSYS 2 10 ADC clock source FSYS 4 11 ADC clock source FSYS 8 3 2 ETGTYP 1 0 External trigger type select When ADCEX ADCCON1 1 is set these bits select which condition triggers ADC conve...

Page 302: ...s enabled 0 ADC result comparator trig ADCF Disabled 1 ADC result comparator trig ADCF Enabled Note After this bit is enabled and ADC start is triggered the ADC keeps converting The register ADCRH and...

Page 303: ...trigger delay time ADC F ADCDLY Note that this field is valid only when ADCEX ADCCON1 1 is set User should not modify ADCDLY during PWM run time if selecting PWM output as the external ADC trigger sou...

Page 304: ...eset Value ADCMPL CEH page 0 0000_0000b 7 6 5 4 3 2 1 0 ADCMP 3 0 W R Bit Name Description 3 0 ADCMP 3 0 ADC compare low byte The least significant 4 bits of the ADC compare value stores in this regis...

Page 305: ...rd wired 0 it allows toggling of the DPS bit by incrementing AUXR0 without interfering with other bits in the register MOV R0 64 number of bytes to move MOV DPTR D_Addr load destination address INC AU...

Page 306: ...AUXR1 Auxiliary Register 1 Regiser Address Reset Value AUXR1 A2H all pages POR 0000_0000b Software 1U00_0000b nRESET pin U100_0000b Others UUU0_0000b 7 6 5 4 3 2 1 0 SWRF RSTPINF HardF SLOW GF2 UART0...

Page 307: ...MS51 Dec 17 2019 Page 307 of 316 Rev 1 01 MS51 SERIES TECHNICAL REFERENCE MANUAL 7 PACKAGE DIMENSIONS 7 1 TSSOP 20 pin 4 4 x 6 5 x 0 9 mm Figure 7 1 1 TSSOP 20 Package Dimension...

Page 308: ...MS51 Dec 17 2019 Page 308 of 316 Rev 1 01 MS51 SERIES TECHNICAL REFERENCE MANUAL...

Page 309: ...MS51 Dec 17 2019 Page 309 of 316 Rev 1 01 MS51 SERIES TECHNICAL REFERENCE MANUAL 7 2 QFN 20 pin 3 0 x 3 0 x 0 8 mm for MS51XB9AE Figure 7 2 1 QFN 20 Package Dimension for MS51XB9AE...

Page 310: ...MS51 Dec 17 2019 Page 310 of 316 Rev 1 01 MS51 SERIES TECHNICAL REFERENCE MANUAL 7 3 QFN 20 pin 3 0 x 3 0 x 0 6mm for MS51XB9BE Figure 7 3 1 QFN 20 Package Dimension for MS51XB9BE...

Page 311: ...Instruction CY OV AC Instruction CY OV AC ADD X 1 X X CLR C 0 ADDC X X X CPL C X SUBB X X X ANL C bit X MUL 0 X ANL C bit X DIV 0 X ORL C bit X DA A X ORL C bit X RRC A X MOV C bit X RLC A X CJNE X S...

Page 312: ...04 1 1 12 INC Rn 08 0F 1 3 4 INC direct 05 2 4 3 INC Ri 06 07 1 5 2 4 INC DPTR A3 1 1 24 DEC A 14 1 1 12 DEC Rn 18 1F 1 3 4 DEC direct 15 2 4 3 DEC Ri 16 17 1 5 2 4 MUL AB A4 1 4 12 DIV AB 84 1 4 12...

Page 313: ...direct data 75 3 3 8 MOV Ri A F6 F7 1 3 4 MOV Ri direct A6 A7 2 4 6 MOV Ri data 76 77 2 3 6 MOV DPTR data16 90 3 3 8 MOVC A A DPTR 93 1 4 6 MOVC A A PC 83 1 4 6 MOVX A Ri 1 E2 E3 1 5 4 8 MOVX A DPTR 1...

Page 314: ...0 3 5 4 8 JBC bit rel 10 3 5 4 8 CJNE A direct rel B5 3 5 4 8 CJNE A data rel B4 3 4 6 CJNE Rn data rel B8 BF 3 4 6 CJNE Ri data rel B6 B7 3 6 4 DJNZ Rn rel D8 DF 2 4 6 DJNZ direct rel D5 3 5 4 8 Note...

Page 315: ...TORY Date Revision Description 2019 01 22 1 00 Initial version 2019 12 17 1 01 Section 4 1 2 Modified MS51XB9BE pin assignment Section 6 5 Added SPROM description Section 19 1 3 Added note in ADC resu...

Page 316: ...but is not limited to equipment for surgical implementation atomic energy control instruments airplane or spaceship instruments the control or operation of dynamic brake or safety systems designed for...

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