MS51
Dec. 17, 2019
Page
162
of 316
Rev 1.01
M
S51
SE
RIES
TE
CHNICA
L REF
ERE
N
CE MA
NU
A
L
AUXR1
– Auxiliary Register 1
Regiser
Address
Reset Value
AUXR1
A2H, all pages
POR 0000_0000b,
Software 1U00_0000b
nRESET pin U100_0000b
Others UUU0_0000b
7
6
5
4
3
2
1
0
SWRF
RSTPINF
HardF
HardFInt
GF2
-
0
DPS
R/W
R/W
R/W
R/W
R/W
-
R
R/W
Bit
Name
Description
6
RSTPINF
External reset flag
When the MCU is reset by the external reset, this bit will be set via hardware. It is recommended
that the flag be cleared via software.
5
HardF
Hard Fault reset flag
Once CPU fetches instruction address over flash size while EHFI (EIE1.4)=0, MCU will reset
and this bit will be set via hardware. It is recommended that the flag be cleared via software.
Note:
If MCU run in OCD debug mode and OCDEN = 0, Hard fault reset will disable. Only
HardF flag be asserted.
6.2.7
Watchdog Timer Reset
The WDT is a free running timer with programmable time-out intervals and a dedicated internal clock
source. User can clear the WDT at any time, causing it to restart the counter. When the selected time-
out occurs but no software response taking place for a while, the WDT will reset the system directly
and CPU will begin execution from 0000H.
Once a reset due to WDT occurs, the WDT reset flag WDTRF (WDCON.3) will be set. This bit keeps
unchanged after any reset other than a power-on reset or WDT reset itself. User can clear WDTRF via
software.
