MS51
Dec. 17, 2019
Page
168
of 316
Rev 1.01
M
S51
SE
RIES
TE
CHNICA
L REF
ERE
N
CE MA
NU
A
L
Interrupt Source
Vector
Address
Interrupt Flag(S)
Enable Bit
Natural
Priority
Priority Control
Bits
Power-Down
Wake-Up
Timer 1
001BH
TF1[2]
ET1
9
PT1, PT1H
No
Serial port 0
0023H
RI + TI
ES
10
PS, PSH
No
Fault Brake event
0073h
FBF (FBD.7)
EFB
11
PFB, PFBH
No
SPI
004Bh
SPIF (SPSR.7) +
MODF (SPSR.4) +
SPIOVF (SPSR.5)
ESPI
12
PSPI, PSPIH
No
Timer 2
002BH
TF2[2]
ET2
13
PT2, PT2H
No
Input capture
0063H
CAPF[2:0]
(CAPCON0[2:0])
ECAP
14
PCAP, PCAPH
No
PWM interrupt
006BH
PWMF
EPWM
15
PPWM, PPWMH
No
Serial port 1
007BH
RI_1 + TI_1
ES_1
16
PS_1, PSH_1
No
Timer 3
0083H
TF3[2] (T3CON.4)
ET3
17
PT3, PT3H
No
Self Wake-up Timer
008BH
WKTF (WKCON.4)
EWKT
18
PWKT, PWKTH
Yes
Note:
1. While the external interrupt pin is set as edge triggered (Itx = 1), its own flag Iex will be automatically cleared if
the interrupt service routine (ISR) is executed. While as level triggered (Itx = 0), Iex follows the inverse of
respective pin state. It is not controlled via software.
2. TF0, TF1, or TF3 is automatically cleared if the interrupt service routine (ISR) is executed. On the contrary,
be aware that TF2 is not.
3. If level triggered is selected for pin interrupt channel n, PIFn flag reflects the respective channel state. It is not
controlled via software.
Table 6.2-3 Characteristics of Each Interrupt Source
6.2.14
Interrupt Service
The interrupt flags are sampled every system clock cycle. In the same cycle, the sampled interrupts
are polled and their priority is resolved. If certain conditions are met then the hardware will execute an
internally generated LCALL instruction, which will vector the process to the appropriate interrupt vector
address. The conditions for generating the LCALL are,
1. An interrupt of equal or higher priority is not currently being serviced.
2. The current polling cycle is the last cycle of the instruction currently being executed.
3. The current instruction does not involve a write to any enabling or priority setting bits and is not a
RETI.
If any of these conditions are not met, then the LCALL will not be generated. The polling cycle is
repeated every system clock cycle. If an interrupt flag is active in one cycle but not responded to for
the above conditions are not met, if the flag is not still active when the blocking condition is removed,
the denied interrupt will not be serviced. This means that the interrupt flag, which was once active but
not serviced is not remembered. Every polling cycle is new.
The processor responds to a valid interrupt by executing an LCALL instruction to the appropriate
service routine. This action may or may not clear the flag, which caused the interrupt according to
different interrupt source. The hardware LCALL behaves exactly like the software LCALL instruction.
This instruction saves the Program Counter contents onto the Stack RAM but does not save the
Program Status Word (PSW). The PC is reloaded with the vector address of that interrupt, which
caused the LCALL. Execution continues from the vectored address until an RETI instruction is
executed. On execution of the RETI instruction, the processor pops the Stack and loads the PC with
the contents at the top of the stack. User should take care that the status of the stack. The processor
does not notice anything if the stack contents are modified and will proceed with execution from the
address put back into PC. Note that a simple RET instruction would perform exactly the same process
as a RETI instruction, but it would not inform the Interrupt controller that the interrupt service routine is
