MS51
Dec. 17, 2019
Page
294
of 316
Rev 1.01
M
S51
SE
RIES
TE
CHNICA
L REF
ERE
N
CE MA
NU
A
L
Bit
Name
Description
2
PIO12
P0.5/PWM2 pin function select
0 = P0.5/PWM2 pin functions as P0.5.
1 = P0.5/PWM2 pin functions as PWM2 output.
1
PIO11
P1.4/PWM1 pin function select
0 = P1.4/PWM1 pin functions as P1.4.
1 = P1.4/PWM1 pin functions as PWM1 output.
PDTEN
– PWM Dead-time Enable
Regiser
Address
Reset Value
PDTEN
F9H, all page, TA protected
0000_0000b
7
6
5
4
3
2
1
0
-
-
-
PDTCNT.8
-
PDT45EN
PDT23EN
PDT01EN
-
-
-
R/W
-
R/W
R/W
R/W
Bit
Name
Description
4
PDTCNT8
PWM dead-time counter bit 8
See PDTCNT register.
2
PDT45EN
PWM4/5 pair dead-time insertion enable
This bit is valid only when PWM4/5 is under complementary mode.
0 = No delay on GP4/GP5 pair signals.
1 = Insert dead-time delay on the rising edge of GP4/GP5 pair signals.
1
PDT23EN
PWM2/3 pair dead-time insertion enable
This bit is valid only when PWM2/3 is under complementary mode.
0 = No delay on GP2/GP3 pair signals.
1 = Insert dead-time delay on the rising edge of GP2/GP3 pair signals.
0
PDT01EN
PWM0/1 pair dead-time insertion enable
This bit is valid only when PWM0/1 is under complementary mode.
0 = No delay on GP0/GP1 pair signals.
1 = Insert dead-time delay on the rising edge of GP0/GP1 pair signals.
PDTCNT
– PWM Dead-time Counter
Regiser
Address
Reset Value
PDTCNT
FAH, all page, TA protected
0000_0000b
7
6
5
4
3
2
1
0
PDTCNT[7:0]
R/W
Bit
Name
Description
7:0
PDTCNT[7:0]
PWM dead-time counter low byte
This 8-bit field combined with PDTEN.4 forms a 9-bit PWM dead-time counter PDTCNT. This
counter is valid only when PWM is under complementary mode and the correspond PDTEN
bit for PWM pair is set.
PWM dead-time =
SYS
F
1
PDTCNT
.
Note that user should not modify PDTCNT during PWM run time.
PMEN
– PWM Mask Enable
