CHAPTER 10 SERIAL INTERFACE FUNCTION
294
Figure 10-33. Error Tolerance (when k = 0), including Sampling Errors
Basic timing
(clock cycle T)
START
D0
D7
P
STOP
High-speed clock
(clock cycle T’)
enabling normal
reception
START
D0
D7
P
STOP
Low-speed clock
(clock cycle T”)
enabling normal
reception
START
D0
D7
P
STOP
32T
64T
256T
288T
320T
352T
Ideal
sampling
point
304T
336T
30.45T
60.9T
304.5T
15.5T
15.5T
0.5T
Sampling error
33.55T
67.1T
301.95T
335.5T
Remark
T: 5-bit counter’s source clock cycle
Baud rate error tolerance (when k = 0) =
×
100 = 4.8438 (%)
±
15.5
320
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