CHAPTER 7 TIMER/COUNTER FUNCTION
151
Figure 7-2. Format of 16-Bit Timer Mode Control Register 0, 1 (TMC0, TMC1) (1/2)
After reset: 00H R/W
Address: FFFFF208H, FFFFF218H
7
6
5
4
3
2
1
0
TMCn
0
0
0
0
TMCn3
TMCn2
TMCn1
OVFn
(n = 0, 1)
TMCn3
TMCn2
TMCn1
Selects Operation
Mode and Clear Mode
Selects TOn Output
Timing
Generation of Interrupt
0
0
0
Operation stops (TMn is
cleared to 0).
Not affected.
Does not generate.
0
0
1
0
1
0
Free-running mode
Coincidence between
TMn and CRn0 or
coincidence between
TMn and CRn1
0
1
1
Coincidence between
TMn and CRn0,
coincidence between
TMn and CRn1, or valid
edge of TIn0
1
0
0
Clears and starts at
valid edge of TIn0.
Coincidence between
TMn and CRn0 or
coincidence between
TMn and CRn1
1
0
1
Coincidence between
TMn and CRn0,
coincidence between
TMn and CRn1, or valid
edge of TIn0
1
1
0
Clears and starts on
coincidence between
TMn and CRn0.
Coincidence between
TMn and CRn0 or
coincidence between
TMn and CRn1
1
1
1
Coincidence between
TMn and CRn0,
coincidence between
TMn and CRn1, or valid
edge of TIn0
Generates on
coincidence between
TMn and CRn0 and
coincidence between
TMn and CRn1.
Summary of Contents for V850/SA1 mPD703015
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