
CHAPTER 10 SERIAL INTERFACE FUNCTION
231
Figure 10-11. Format of IIC Clock Select Register (IICCL0) (2/2)
SMC
DFC
Note
CL1
CL0
Operation Mode Switching
1
×
0
0
fxx/24
1
×
0
1
fxx/24
1
×
1
0
fxx/48
1
×
1
1
TM2 output/18
0
0
0
0
fxx/44
0
0
0
1
fxx/86
0
0
1
0
fxx/172
0
0
1
1
TM2 output/66
0
1
0
0
fxx/46
0
1
0
1
fxx/88
0
1
1
0
fxx/176
0
1
1
1
TM2 output/68
Note
The digital filter (DFC) can be used when in high-speed mode. Response time is slower when the
digital filter is used.
Remark
×
: don’t care
(4) IIC shift register (IIC0)
This register is used for serial transmission/reception (shift operations) that are synchronized with the serial
clock. It can be read from or written to in 8-bit units, but data should not be written to IIC0 during a data
transfer.
After reset : 00H
R/W
Address: FFFFF348H
7
6
5
4
3
2
1
0
IIC0
(5) Slave address register (SVA0)
This register holds the I
2
C bus’s slave addresses.
It can be read from or written to in 8-bit units, but bit 0 should be fixed as “0”.
After reset : 00H
R/W
Address: FFFFF346H
7
6
5
4
3
2
1
0
SVA0
0
Summary of Contents for V850/SA1 mPD703015
Page 2: ...2 MEMO ...
Page 100: ...100 MEMO ...
Page 144: ...144 MEMO ...
Page 200: ...200 MEMO ...
Page 328: ...328 MEMO ...
Page 356: ...356 MEMO ...
Page 358: ...358 MEMO ...
Page 368: ...368 MEMO ...
Page 374: ...374 MEMO ...
Page 382: ...382 MEMO ...