NEC V850/SA1 mPD703015, Preliminary User'S Manual

Page: 228 / 387

CHAPTER 10 SERIAL INTERFACE FUNCTION
228
Figure 10-10. Format of IIC Status Register (IICS0) (2/3)
EXC Detection of Extension Code Reception
0 Extension code was not received.
1 Extension code was received.
Condition for clearing (EXC = 0) Condition for setting (EXC = 1)
•
When a start condition is detected
•
When a stop condition is detected
•
Cleared by LREL = 1
•
When IICE changes from 1 to 0
•
When RESET is input
•
When the high-order four bits of the received address
data is either “0000” or “1111” (set at the rising edge of
the eighth clock).
COI Detection of Matching Addresses
0 Addresses do not match.
1 Addresses match.
Condition for clearing (COI = 0) Condition for setting (COI = 1)
•
When a start condition is detected
•
When a stop condition is detected
•
Cleared by LREL = 1
•
When IICE changes from 1 to 0
•
When RESET is input
•
When the received address matches the local address
(SVA0) (set at the rising edge of the eighth clock).
TRC Detection of Transmit/Receive Status
0 Receive status (other than transmit status). The SDA line is set for high impedance.
1 Transmit status. The value in the SO latch is enabled for output to the SDA line (valid starting at the falling
edge of the first byte’s ninth clock).
Condition for clearing (TRC = 0) Condition for setting (TRC = 1)
•
When a stop condition is detected
•
Cleared by LREL = 1
•
When IICE changes from 1 to 0
•
Cleared by WREL = 1
•
When ALD changes from 0 to 1
•
When RESET is input
Master
•
When “1” is output to the first byte’s LSB (transfer
direction specification bit)
Slave
•
When a start condition is detected
When not used for communication
Master
•
When a start condition is generated
Slave
•
When “1” is input by the first byte’s LSB (transfer
direction specification bit)
Remark LREL : Bit 6 of IIC control register (IICC0)
IICE : Bit 7 of IIC control register (IICC0)