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CHAPTER 9 WATCHDOG TIMER
204
(2) Watchdog timer clock selection register (WDCS)
This register selects the overflow times of the watchdog timer and the interval timer.
WDCS is set by an 8-bit memory manipulation instruction.
RESET input sets WDCS to 00H.
Figure 9-3. Format of Watchdog Timer Clock Selection Register (WDCS)
After reset: 00H
R/W
Address: FFFFF382H
7
6
5
4
3
2
1
0
WDCS
0
0
0
0
0
WDCS2
WDCS1
WDCS0
WDCS2
WDCS1
WDCS0
Watchdog Timer/Interval Timer Overflow Time
Note
0
0
0
2
14
/fxx (964
µ
s)
0
0
1
2
15
/fxx (1.928 ms)
0
1
0
2
16
/fxx (3.855 ms)
0
1
1
2
17
/fxx (7.710 ms)
1
0
0
2
18
/fxx (15.42 ms)
1
0
1
2
19
/fxx (30.84 ms)
1
1
0
2
20
/fxx (61.68 ms)
1
1
1
2
22
/fxx (246.7 ms)
Note
Parenthesized values apply when fxx = 17 MHz.
Summary of Contents for V850/SA1 mPD703015
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