NEC V850/SA1 mPD703015 Preliminary User'S Manual Download Page 111

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CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION

111

Figure 5-6. Maskable Interrupt Processing

Maskable interrupt request

Interrupt processing

EIPC
EIPSW
ECR. EICC
PSW. EP
PSW. ID
PC

INTC accepted

CPU processing

Mask?

Yes

PSW. ID = 0

Priority higher than

that of interrupt currently

processed?

Interrupt request pending

PSW. NP

PSW. ID

Interrupt request pending

INT input

Yes

Priority higher

than that of other interrupt

request?

Highest default

priority of interrupt requests

with the same priority?

Interrupt enable mode?

restored PC
PSW
exception code
0
1
handler address

The INT input masked by the interrupt controllers and the INT input that occurs while the other interrupt is being

processed (when PSW.NP = 1 or PSW.ID = 1) are internally pended by the interrupt controller. When the interrupts

are unmasked, or when PSW.NP = 0 and PSW.ID = 0 by using the RETI and LDSR instructions, the pending INT

input starts the new maskable interrupt processing.

Summary of Contents for V850/SA1 mPD703015

Page 1: ...al µ µ µ µPD703015 µ µ µ µPD703015Y µ µ µ µPD70F3017 µ µ µ µPD70F3017Y V850 SA1 TM 32 16 Bit Single Chip Microcontrollers Hardware 1997 Printed in Japan Document No U12768EJ2V0UM00 2nd edition Date Published June 1998 N CP K ...

Page 2: ...2 MEMO ...

Page 3: ... be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to VDD or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged...

Page 4: ...semiconductor devices the possibility of defects cannot be eliminated entirely To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device customers must incorporate sufficient safety measures in its design such as redundancy fire containment and anti failure features NEC devices are classified into the following three quality grades Standard S...

Page 5: ...cs Germany GmbH Duesseldorf Germany Tel 0211 65 03 02 Fax 0211 65 03 490 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Italiana s r 1 Milano Italy Tel 02 66 75 41 Fax 02 66 75 42 99 NEC Electronics Germany GmbH Benelux Office Eindhoven The Netherlands Tel 040 2445845 Fax 040 2444580 NEC Electronics France S A Velizy Villacoublay France Tel 01 30 67 58 ...

Page 6: ...er Mode Register 0 PRM0 Figure 7 6 Format of Prescaler Mode Register 1 PRM1 Figure 7 10 Control register Settings in PPG Output Operation p 162 Figure 7 13 has been modified p 164 TIn0 has been modified in Figure 7 15 CRn1 Capture Operation with Rising Edge Specified p 164 p 166 p 167 The following figures have been modified Figure 7 16 Timing of Pulse Width Measurement with Free Running Counter w...

Page 7: ...knowledge of electricity logical circuits and microcontrollers To find the details of a register whose name is known Refer to APPENDIX A REGISTER INDEX To find the details of a function etc whose name is known Refer to APPENDIX C INDEX To understand the details of instruction functions Refer to V850 Family User s Manual Architecture To understand the overall functions of the V850 SA1 Read this man...

Page 8: ...1 Hardware User s Manual This manual Related documents for development tool user s manual Document Name Document No IE 703002 MC In circuit emulator U11595E IE 703017 MC EM1 In circuit emulator option board U12898E CA850 C compiler package Operation UNIX based U11013E Operation Windows based U11068E Assembly Language U10543E C Language U11010E Project Manager U11991E ID850 C source debugger Operat...

Page 9: ...3 CPU FUNCTIONS 53 3 1 Features 53 3 2 CPU Register Set 54 3 2 1 Program register set 55 3 2 2 System register set 56 3 3 Operation Modes 58 3 4 Address Space 59 3 4 1 CPU address space 59 3 4 2 Image virtual address space 60 3 4 3 Wrap around of CPU address space 61 3 4 4 Memory map 62 3 4 5 Area 63 3 4 6 External expansion mode 69 3 4 7 Recommended use of address space 72 3 4 8 Peripheral I O re...

Page 10: ...ration 105 5 2 2 Restore 107 5 2 3 NP flag 108 5 2 4 Noise elimination circuit of NMI pin 108 5 2 5 Edge detection function of NMI pin 109 5 3 Maskable Interrupts 110 5 3 1 Operation 110 5 3 2 Restore 112 5 3 3 Priorities of maskable interrupts 113 5 3 4 Interrupt control register xxICn 117 5 3 5 In service priority register ISPR 119 5 3 6 Maskable interrupt status flag 119 5 3 7 Watchdog timer mo...

Page 11: ...as interval timer 16 bits 158 7 2 2 PPG output operation 160 7 2 3 Pulse width measurement 161 7 2 4 Operation as external event counter 168 7 2 5 Operation to output square wave 169 7 2 6 Operation to output one shot pulse 171 7 2 7 Cautions 175 7 3 8 bit Timer TM2 TM5 178 7 3 1 Functions 178 7 3 2 Configuration 179 7 3 3 Timer n control register 181 7 4 Operation 185 7 4 1 Operating as an interv...

Page 12: ...ons 232 10 3 4 I 2 C bus definitions and control methods 233 10 3 5 I 2 C interrupt requests INTIIC0 240 10 3 6 Interrupt request INTIIC0 generation timing and wait control 260 10 3 7 Address match detection method 261 10 3 8 Error detection 262 10 3 9 Extension code 262 10 3 10 Arbitration 263 10 3 11 Wake up function 265 10 3 12 Communication reservation 266 10 3 13 Other cautions 270 10 3 14 Co...

Page 13: ...ration 326 13 5 Usage 327 13 6 Notes 327 CHAPTER 14 PORT FUNCTION 329 14 1 Port Configuration 329 14 2 Port Pin Function 329 14 2 1 Port 0 329 14 2 2 Port 1 333 14 2 3 Port 2 336 14 2 4 Port 3 339 14 2 5 Ports 4 and 5 341 14 2 6 Port 6 343 14 2 7 Ports 7 and 8 345 14 2 8 Port 9 346 14 2 9 Port 10 348 14 2 10 Port 11 350 14 2 11 Port 12 353 CHAPTER 15 RESET FUNCTION 357 15 1 General 357 15 2 Pin Op...

Page 14: ... 364 16 5 6 Power supply 364 16 6 Programming Method 365 16 6 1 Flash memory control 365 16 6 2 Flash memory programming mode 365 16 6 3 Selection of communication mode 366 16 6 4 Communication command 366 16 6 5 Resources used 367 APPENDIX A REGISTER INDEX 369 APPENDIX B LIST OF INSTRUTION SET 375 APPENDIX C INDEX 383 ...

Page 15: ...eously Generated 116 5 10 Interrupt Control Register xxICn Format 117 5 11 Inservice Priority Register ISPR Format 119 5 12 Watchdog Timer Mode Register WDTM Format 120 5 13 Software Exception Processing 122 5 14 RETI Instruction Processing 123 5 15 Exception Trap Processing 125 5 16 RETI Instruction Processing 126 5 17 Pipeline Operation at Interrupt Request Acknowledge 130 6 1 Format of Processo...

Page 16: ... Square Wave Output Mode 170 7 25 Timing of Square Wave Output Operation 171 7 26 Control Register Settings for One Shot Pulse Output with Software Trigger 172 7 27 Timing of One Shot Pulse Output Operation with Software Trigger 173 7 28 Control Register Settings for One Shot Pulse Output with External Trigger 174 7 29 Timing of One Shot Pulse Output Operation with External Trigger with rising edg...

Page 17: ...ction Specification 235 10 17 ACK Signal 236 10 18 Stop Condition 237 10 19 Wait Signal 238 10 20 Arbitration Timing Example 264 10 21 Communication Reservation Timing 267 10 22 Timing for Accepting Communication Reservations 268 10 23 Communication Reservation Flow Chart 269 10 24 Master Operation Flow Chart 271 10 25 Slave Operation Flow Chart 272 10 26 Example of Master to Slave Communication w...

Page 18: ...put Port Mode Register RTPM 324 13 4 Format of Real Time Output Port Control Register RTPC 325 13 5 Example of Operation Timing of RTO when EXTR 0 BYTE 0 326 14 1 Format of Port 0 P0 329 14 2 Format of Port 0 Mode Register PM0 331 14 3 Format of Pull up Resistance Option Register 0 PU0 331 14 4 Format of Rising Edge Enable Register EGP0 332 14 5 Format of Falling Edge Enable Register EGN0 332 14 6...

Page 19: ...sistance Option Register 10 PU10 350 14 27 Format of Port 10 Function Register PF10 350 14 28 Format of Port 11 P11 351 14 29 Format of Port 11 Mode Register PM11 352 14 30 Format of Pull up Resistance Option Register 11 PU11 352 14 31 Format of Port 12 P12 353 14 32 Format of Port 12 Mode Register PM12 354 14 33 Format of Port 12 Mode Control Register PMC12 355 15 1 System Reset Timing 357 ...

Page 20: ...mer 199 9 1 Runaway Detection Time for Watchdog Timer 202 9 2 Interval Time 202 9 3 Watchdog Timer Configuration 203 9 4 Runaway Detection Time of Watchdog Timer 206 9 5 Interval Time of Interval Timer 207 10 1 Configuration of CSIn 210 10 2 Configuration of I 2 C 220 10 3 INTIIC0 Timing and Wait Control 260 10 4 Extension Code Bit Definitions 262 10 5 Status during Arbitration and Interrupt Reque...

Page 21: ...high level of cost performance suitable for applications ranging from low power camcorders and other AV equipment to portable telephone equipment such as cellular phones and PHS phone systems 1 2 Features Number of instructions 74 Minimum instruction execution time 59 ns when main system clock fXX is operating at 17 MHz 30 5 µs when subsystem clock fXT is operating at 32 768 kHz General purpose re...

Page 22: ...nnection enabled Watch timer When operating under subsystem or main system clock 1 channel Watchdog timer 1 channel Serial interface SIO Asynchronous serial interface UART Clock synchronized serial interface CSI I 2 C bus interface I 2 C µPD703015Y or 70F3017Y only UART 1 ch CSI 1 ch UART CSI 1 ch I 2 C CSI 1 ch UART dedicated baud rate generator 2 channels A D converter 10 bit resolution 12 chann...

Page 23: ... 12 12 mm Mask ROM µPD703015YGC 8EU 100 pin plastic LQFP fine pitch 14 14 mm Mask ROM µPD703015YS1 YJC 121 pin fine pitch BGA 12 12 mm Mask ROM µPD70F3017GC 8EU 100 pin plastic LQFP fine pitch 14 14 mm Flash memory µPD70F3017S1 YJC 121 pin fine plastic BGA 12 12 mm Flash memory µPD70F3017YGC 8EU 100 pin plastic LQFP fine pitch 14 14 mm Flash memory µPD70F3017YS1 YJC 121 pin fine pitch BGA 12 12 mm...

Page 24: ...P0 A5 P101 RTP1 A6 P102 RTP2 A7 P103 RTP3 A8 P104 RTP4 A9 P105 RTP5 A10 P106 RTP6 A11 P20 SI2 P15 SCK1 ASCK0 P14 SO1 TXD0 P13 SI1 RXD0 P12 SCK0 SCL Note 2 P11 SO0 P10 SI0 SDA Note 2 P07 INTP6 P06 INTP5 RTPTRG P05 INTP4 ADTRG P04 INTP3 P03 INTP2 P02 INTP1 P01 INTP0 P00 NMI P83 ANI11 P82 ANI10 P81 ANI9 P80 ANI8 P77 ANI7 P76 ANI6 P75 ANI5 P74 ANI4 P73 ANI3 P72 ANI2 P107 RTP7 A12 P110 A1 P111 A2 P112 ...

Page 25: ... P44 A8 P00 C2 P23 E3 P30 H12 P53 L7 P90 N1 P107 A9 P81 C3 VSS E11 AVDD H13 P54 L8 P120 N2 P110 A10 P76 C4 P24 E12 P64 J1 IC VPP Note L9 P93 N3 P112 A11 P73 C5 P07 E13 P65 J2 IC VPP Note L10 P96 N4 VDD A12 P72 C6 P04 F1 P26 J3 P100 L11 BVSS N5 XT1 A13 AVSS C7 P01 F2 P27 J11 P52 L12 BVSS N6 VSS B1 P21 C8 P82 F3 P33 J12 P50 L13 BVSS N7 VSS B2 P14 C9 P77 F11 P63 J13 P51 M1 P106 N8 CLKOUT B3 VSS C10 P...

Page 26: ...lock CLKOUT Clock Output SCL Serial Clock DSTB Data Strobe SDA Serial Data HLDAK Hold Acknowledge SI0 SI2 Serial Input HLDRQ Hold Request SO0 SO2 Serial Output IC Internally Connected TI00 TI01 TI10 TI11 TI2 TI5 INTP0 INTP6 Interrupt Request From Peripherals Timer Input LBEN Lower Byte Enable TO0 TO5 Timer Output NMI Non maskable Interrupt Request TXD0 TXD1 Transmit Data P00 P07 Port0 UBEN Upper B...

Page 27: ...TO0 TO1 INTP0 INTP6 SIO INTC Note 1 Note 2 ROM CPU BCU RAM Timer counter 16 bit timer TM0 TM1 8 bit timer TM2 to TM5 CSI0 I2 CNote 4 CSI1 UART0 CSI2 UART1 DMAC 3ch Watch timer Watchdog timer Ports RTP A D converter CG PC 32 bit barrel shifter System register General purpose registers 32 bits 32 Multiplier 16 16 32 ALU Instruction queue HLDRQ P96 HLDAK P95 ASTB P94 DSTB RD P93 R W WRH P92 UBEN P91 ...

Page 28: ...r voltage level compared to the VDD and VSS pins 3 ROM This consists of a 128 Kbyte mask ROM or a 256 Kbyte flash memory mapped to the address space starting at 00000000H Both types of memory are accessed by the CPU in one clock cycle when an instruction is fetched 4 RAM This consists of a 4 Kbyte RAM mapped to the address space starting at FFFFE000H if the device includes mask ROM or an 8 Kbyte R...

Page 29: ...des two kinds of serial interfaces an asynchronous serial interface UART and a clock synchronized serial interface CSI These plus the I 2 C bus interface comprise four channels One of these channels is switchable between the UART and CSI and another is switchable between CSI and I 2 C while the remaining two channels are fixed one as UART and one as CSI For UART data is transferred via the TXDn an...

Page 30: ...6 bit I O Serial interface P2 8 bit I O Serial interface timer output P3 8 bit I O Timer I O external address bus P4 8 bit I O External address data bus P5 P6 6 bit I O External address bus P7 8 bit input A D converter analog input P8 4 bit input P9 7 bit I O External bus interface control signal I O P10 8 bit I O Real time output port external address bus P11 4 bit I O 1 bit input External addres...

Page 31: ...I P01 INTP0 P02 INTP1 P03 INTP2 P04 INTP3 P05 INTP4 ADTRG P06 INTP5 RTPTRG P07 INTP6 P10 I O Yes SI0 SDA P11 SO0 P12 SCK0 SCL P13 SI1 RXD0 P14 SO1 TXD0 P15 SCK1 ASCK0 P20 I O Yes SI2 P21 SO2 P22 SCK2 P23 RXD1 P24 TXD1 P25 ASCK1 P26 TI2 TO2 P27 TI3 TO3 Remark PULL on chip pull up resistor Port 1 6 bit I O port Input output mode can be specified bitwise Port 2 8 bit I O port Input output mode can be...

Page 32: ... P47 AD7 P50 I O No AD8 P51 AD9 P52 AD10 P53 AD11 P54 AD12 P55 AD13 P56 AD14 P57 AD15 P60 I O No A16 P61 A17 P62 A18 P63 A19 P64 A20 P65 A21 Remark PULL on chip pull up resistor Port 3 8 bit I O port Input output mode can be specified bitwise Port 4 8 bit I O port Input output mode can be specified bitwise Port 5 8 bit I O port Input output mode can be specified bitwise Port 6 6 bit I O port Input...

Page 33: ...3 A8 P104 RTP4 A9 P105 RTP5 A10 P106 RTP6 A11 P107 RTP7 A12 P110 I O Yes A1 P111 A2 P112 A3 P113 A4 P114 Input No XT1 P120 I O No WAIT Remark PULL on chip pull up resistor Port 7 8 bit input port Input mode can be specified bitwise Port 8 4 bit input port Input mode can be specified bitwise Port 9 7 bit I O port Input output mode can be specified bitwise Port 10 8 bit I O port Input output mode ca...

Page 34: ...P94 AVDD Positive power supply for A D converter AVREF Input Reference voltage input for A D converter AVSS Ground potential for A D converter BVDD Positive power supply for bus interface BVSS Ground potential for bus interface CLKOUT Output Internal system clock output DSTB Output No External data strobe signal output P93 RD HLDAK Output No Bus hold acknowledge output P95 HLDRQ Input No Bus hold ...

Page 35: ...al count clock input for TM0 P30 TI01 External capture trigger input for TM0 P31 TI10 Shared as external capture trigger input and external count clock input for TM1 P32 TI11 External capture trigger input for TM1 P33 TI2 External count clock input for TM2 P26 TO2 TI3 External count clock input for TM3 P27 TO3 TI4 External count clock input for TM4 P36 TO4 A15 TI5 External count clock input for TM...

Page 36: ...utput No High order byte write strobe signal output for external data bus P92 R W WRL Low order byte write strobe signal output for external data bus P90 LBEN X1 Input No Resonator connection for main clock X2 XT1 Input No Resonator connection for subsystem clock P114 XT2 IC Internally connected µPD703015 703015Y only Remark PULL on chip pull up resistor ...

Page 37: ... Hi Z Hi Z Hi Z Held Hi Z Held LBEN UBEN Hi Z Hi Z Hi Z Held Hi Z Held R W Hi Z Hi Z Hi Z H Hi Z H DSTB WRL WRH RD Hi Z Hi Z Hi Z H Hi Z H ASTB Hi Z Hi Z Hi Z H Hi Z H HLDRQ Operating Operating Operating HLDAK Hi Z Hi Z Hi Z Operating L Operating WAIT CLKOUT Hi Z L L Operating Note Operating Note Operating Note Note L when in clock output inhibit mode Remark Hi Z High impedance Held State is held ...

Page 38: ... 0 mode register PM0 b Control modes P00 to P07 can be set bitwise to port mode or a control mode according to the contents of the external interrupt rising edge enable register EGP0 or the external interrupt falling edge enable register EGN0 i NMI Non maskable Interrupt Request input This pin accepts input of non maskable interrupt request signals ii INTP0 to INTP6 Interrupt Request from Peripher...

Page 39: ...he port 1 register P1 or port 1 mode register PM1 i SI0 SI1 Serial Input 0 1 input These pins accept input of the serial receive data of CSI0 and CSI1 ii SO0 SO1 Serial Output 0 1 output These pins accept output of the serial transmit data of CSI0 and CSI1 iii SCK0 SCK1 Serial Clock 0 1 3 state I O These are the serial clock I O pins for CSI0 and CSI1 iv SDA Serial Data I O This is the serial tran...

Page 40: ...cording to the contents of the port 2 register P2 and port 2 mode register PM2 i SI2 Serial Input 2 input This pin accepts input of the CSI2 serial receive data ii SO2 Serial Output 2 output This pin accepts output of the CSI2 serial transmit data iii SCK2 Serial Clock 2 3 state I O This is the CSI2 serial clock I O pin iv RXD1 Receive Data 1 input This is the input pin for UART1 serial receive da...

Page 41: ...tput These pins output pulse signals from timer 0 timer 1 timer 4 and timer 5 iii A13 to A15 Address 13 to 15 output These are address bus that is used for external access These pins operate as A13 to A15 bit address output pins within a 22 bit address The output changes in synchronization with the rising edge of the clock in the T1 state of the bus cycle When the timing sets the bus cycle as inac...

Page 42: ... bus interface power supply pins BVDD and BVSS as a reference a Port mode P50 to P57 can be set bitwise as input or output pins according to the contents of port 5 mode register PM5 b Control mode external expansion mode P50 to P57 can be set as AD8 to AD15 according to the contents of the memory expansion register MM i AD8 to AD15 Address Data 8 to 15 3 state I O These are multiplexed address dat...

Page 43: ...pins are fixed as input pins Port 8 is a 4 bit input only port P70 to P77 and P80 to P83 can function as input ports and can also function as analog input pins for the A D converter when under control mode However they cannot be switched between these input port and analog input pin a Port mode P70 to P77 and P80 to P83 are input only pins b Control mode external expansion mode P70 to P77 are shar...

Page 44: ...to operate as control signal outputs for external memory expansion according to the contents of the memory expansion register MM i LBEN Lower Byte Enable output This is a lower byte enable LBEN signal output pin for an external 16 bit data bus The output changes in synchronization with the rising edge of the clock in the T1 state of the bus cycle When the timing sets the bus cycle as inactive the ...

Page 45: ...vel in synchronization with the falling edge of the clock during the T3 state of the bus cycle Output becomes inactive when the timing sets the bus cycle as inactive vi HLDAK Hold Acknowledge output In this mode this pin is output pin for the acknowledge signal that indicates high impedance status for the address bus data bus and control bus when the V850 SA1 receives a bus hold request The addres...

Page 46: ...according to the contents of the port 10 register P10 and port 10 mode register PM10 i RTP0 to RTP7 Real time Port 0 to 7 output In this mode these pins comprise a real time output port ii A5 to A12 Address 5 to 12 output These are address bus that is used for external access These pins operate as A5 to A12 bit address output pins within a 22 bit address The output changes in synchronization with ...

Page 47: ... contents of port 12 mode register PM12 b Control mode P120 can operate as the WAIT pin according to the contents of port 12 mode control register PMC12 i WAIT Wait input This is the input pin for the control signal used to insert waits into the bus cycle This pin is sampled at the falling edge of the clock during the T2 or TW state of the bus cycle 13 RESET Reset input RESET input is asynchronous...

Page 48: ... bus interface 20 BVSS Ground for Bus Interface This is the ground pin for the bus interface 21 VDD Power Supply These are the positive power supply pins Both VDD pins should be connected to a positive power source 22 VSS Ground These are the ground pins Both VSS pins should be grounded 23 VPP Programming Power Supply This is the positive power supply pin used for flash memory programming mode Thi...

Page 49: ... to VDD or VSS P11 SO0 26 During output leave open P12 SCK0 SCL 10 A P13 SI1 RXD0 8 A P14 SO1 TXD0 26 P15 SCK1 ASCK0 10 A P20 SI2 8 A P21 SO2 26 P22 SCK2 10 A P23 RXD1 8 A P24 TXD1 5 A P25 ASCK1 8 A P26 P27 TI2 TO2 TI3 TO3 P30 P31 TI00 TI01 8 A P32 P33 TI10 TI11 P34 P35 TO0 A13 TO1 A14 5 A P36 TI4 TO4 A15 8 A P37 TI5 TO5 P40 to P47 AD0 to AD7 5 During input connect to BVDD or BVSS P50 to P57 AD8 t...

Page 50: ...STB RD P94 ASTB P95 HLDAK P96 HLDRQ P100 to P107 RTP0 A5 to RTP7 A12 26 During input connect to VDD or VSS P110 to P113 A1 to A4 5 A During output leave open P114 XT1 16 P120 WAIT 5 During input connect to BVDD or BVSS During output leave open AVDD Connect to VDD AVSS Connect to VSS AVREF CLKOUT 4 Leave open RESET 2 VPP Connect to VSS X2 Leave open when external clock is input to 1 pin XT2 16 Leav...

Page 51: ... for high impedance output both P ch and N ch off Type 8 A Type 5 Type 9 pullup enable input enable IN OUT data output disable N ch P ch P ch VDD VDD IN OUT output disable N ch data P ch VDD pullup enable IN OUT data output disable N ch P ch P ch VDD VDD output disable input enable IN OUT data N ch P ch VDD N ch P ch input enable VREF threshold voltage comparator ...

Page 52: ...CTIONS 52 2 2 Type 10 A Type 26 Type 16 pullup enable IN OUT data open drain output disable N ch P ch P ch VDD VDD pullup enable IN OUT data open drain output disable N ch P ch P ch VDD VDD P ch XT1 XT2 feedback cut off ...

Page 53: ...m instruction execution time 58 ns at 17 MHz Address space 4 Mbytes linear Thirty two 32 bit general registers Internal 32 bit architecture Five stage pipeline control Multiplication division instructions Saturated operation instructions Single cycle 32 bit shift instruction Load store instruction with long short format Four types of bit manipulation instructions Set Clear Not Test ...

Page 54: ... r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 Zero Register Reserved for Address Register Interrupt Stack Pointer Stack Pointer SP Global Pointer GP Text Pointer TP Element Pointer EP Link Pointer LP PC Program Counter PSW Program Status Word ECR Exception Cause Register FEPC FEPSW Fatal Error PC Fatal Error PSW EIPC EIPSW Exception Inte...

Page 55: ...gister for generating 32 bit immediate r2 Interrupt stack pointer Stack pointer for interrupt handler r3 Stack pointer Used to generate stack frame when function is called r4 Global pointer Used to access global variable in data area r5 Text pointer Register to indicate the start of the text area Note r6 to r29 Address data variable registers r30 Element pointer Base pointer register when memory i...

Page 56: ...n maskable interrupt or NMI occurs this register will contain information referencing the interrupt source The high order 16 bits of this register are called FECC to which exception code of NMI is set The low order 16 bits are called EICC to which exception code of exception interrupt is set 5 PSW Program status word Program status word is collection flags that indicate program status instruction ...

Page 57: ...ed even if this bit is set ID Indicates that accepting external interrupt request is disabled SAT This flag is set if result of executing saturated operation instruction overflows If overflow does not occur value of previous operation is held CY This flag is set if carry or borrow occurs as result of operation If carry or borrow does not occur it is reset OV This flag is set if overflow occurs dur...

Page 58: ...rnal ROM is started However external expansion mode that connects external device to external memory area is enabled by setting in the memory expansion mode register MM by instruction 2 Flash memory programming mode This mode is provided only to the µPD70F3017 and 70F3017Y The internal flash memory is programmable or erasable when the VPP voltage is applied to VPP pin The state transition to the p...

Page 59: ...ear address space data space during operand addressing data access When referencing instruction addresses a linear address space program space of up to 16 Mbytes is supported Figure 3 1 shows the CPU address space Figure 3 1 CPU Address Space FFFFFFFFH CPU address space Program area 16 Mbyte linear Data area 4 Gbyte linear 01000000H 00FFFFFFH 00000000H ...

Page 60: ...se the higher 8 bits of a 32 bit CPU address are ignored and the CPU address is only seen as a 24 bit external physical address the physical location xx000000H is equally referenced by multiple address values 00000000H 01000000H 02000000H through FE000000H FF000000H Figure 3 2 Image on Address Space FFFFFFFFH FF000000H FEFFFFFFH Image CPU address space Image Image Image Image FE000000H FDFFFFFFH 0...

Page 61: ...e addresses Caution No instruction can be fetched from the 4 Kbyte area of 00FFF000H to 00FFFFFFH because this area is defined as peripheral I O area Therefore do not execute any branch operation instructions in which the destination address will reside in any part of this area 00FFFFFEH 00FFFFFFH 00000000H 00000001H Program space Program space direction direction 2 Data space The result of operan...

Page 62: ...ternal ROM area On chip peripheral I O area Internal RAM area External memory area Internal ROM area Single chip mode Single chip mode external expansion mode 16 MB 1 MB 4 KB xxFFF000H xxFFEFFFH xx100000H xx0FFFFFH xx000000H xxFFC000H xxFFBFFFH xxFFFFFFH Mask ROM internal version xxFFF000H xxFFEFFFH xx100000H xx0FFFFFH xx000000H xxFFE000H xxFFDFFFH 4 KB Mask ROM internal version 12KB Flash memory ...

Page 63: ...00H xx0DFFFFH xx040000H xx03FFFFH xx020000H xx01FFFFH xx000000H Image Image Image Physical internal ROM Internal ROM 01FFFFH 000000H Interrupt exception table Interrupt exception table The V850 SA1 increases the interrupt response speed by assigning handler addresses corresponding to interrupts exceptions The collection of these handler addresses is called an interrupt exception table which is loc...

Page 64: ...0A0H INTP1 000000B0H INTP2 000000C0H INTP3 000000D0H INTP4 000000E0H INTP5 000000F0H INTP6 00000100H INTWTI 00000110H INTTM00 00000120H INTTM01 00000130H INTTM10 00000140H INTTM11 00000150H INTTM2 00000160H INTTM3 00000170H INTTM4 00000180H INTTM5 00000190H INTIIC0 INTCSI0 000001A0H INTSER0 000001B0H INTSR0 INTCSI1 000001C0H INTST0 000001D0H INTCSI2 000001E0H INTSER1 000001F0H INTSR1 00000200H INT...

Page 65: ...memory internal version In the flash memory internal version 12 Kbytes of FFC000H to FFEFFFH is reserved as an internal RAM area The image of FFE000H to FFEFFFH can be seen in the addresses of FFC000H to FFCFFFH xxFFEFFFH xxFFEFFFH xxFFD000H xxFFCFFFH xxFFC000H xxFFE000H Mask ROM internal version Flash memory internal version Internal RAM Internal RAM ImageNote Note The address FFC000H to FFCFFFH ...

Page 66: ...ed the register at the next lowest even address 2n will be accessed 2 If a register that can be accessed in byte units is accessed in half word units the higher 8 bits become undefined if the access is a read operation If a write access is made only the data in the lower 8 bits is written to the register 3 If a register with n address that can be accessed only in halfword units is accessed with a ...

Page 67: ...ical external memory the image of the physical external memory can be seen The internal RAM area and on chip peripheral I O area are not subject to external memory access Figure 3 5 External Memory Area when expanded to 64 K 256 K or 1 Mbytes xxFFFFFFH xx000000H Physical external memory xFFFFH x0000H On chip peripheral I O Internal RAM Image Image Image Internal ROM xxFFBFFFH xx100000H External me...

Page 68: ...d to 4 Mbytes Physical external memory 3FFFFFH 000000H External memory xxFFFFFFH xx000000H On chip peripheral I O Internal RAM Image Image Image Internal ROM xxFFDFFFH xx100000H Mask ROM internal version xxFFFFFFH xx000000H xxFFBFFFH xx100000H Flash memory internal version ...

Page 69: ...ecause the V850 SA1 is fixed to single chip mode in the normal operation mode the port control mode alternate pins become the port mode thereby the external memory cannot be used When the external memory is used external expansion mode specify the MM register by the program 1 Memory expansion mode register MM This register sets the mode of each pin of ports 4 5 6 and 9 In the external expansion mo...

Page 70: ...ternal expansion mode HLDAK P95 HLDRQ P96 MM2 MM1 MM0 Address Space Port 4 Port 5 Port 6 Port 9 0 0 0 Port mode 0 1 1 64 KB AD0 to AD8 to LBEN expansion mode AD7 AD15 UBEN 1 0 0 256 KB A16 R W DSTB expansion mode A17 ASTB 1 0 1 1 MB A18 WRL expansion mode A19 WRH RD 1 1 4 MB A20 expansion mode A21 Others RFU reserved Remark For the details of the operation of each port pin refer to 2 3 Description...

Page 71: ... 00H W Address FFFFF068H Symbol 7 6 5 4 3 2 1 0 MAM 0 0 0 0 0 MAM2 MAM1 MAM0 MAM2 MAM1 MAM0 Address Space Port 11 Port 10 Port 3 0 0 0 Port mode 0 1 0 32 bytes A1 A4 0 1 1 512 bytes A5 A8 1 0 0 8 Kbytes A9 A12 1 0 1 16 Kbytes A13 1 1 0 32 Kbytes A14 1 1 1 64 Kbytes A15 Caution Debugging the memory address output mode register MAM an in circuit emulator is not available Also setting the MAM registe...

Page 72: ...ot required To enhance the efficiency of using the pointer in connection with the memory map of the V850 SA1 the following points are recommended 1 Program space Of the 32 bits of the PC program counter the higher 8 bits are fixed to 0 and only the lower 24 bits are valid Therefore a contiguous 16 Mbyte space starting from address 00000000H unconditionally corresponds to the memory map of the prog...

Page 73: ...e can be accessed with one pointer The zero register r0 is a register set to 0 by the hardware and eliminates the need for additional registers for the pointer Internal ROM area On chip peripheral I O area External memory area Internal RAM area 4 KB 4 KB 24 KB 0001FFFFH 00007FFFH 0001FFFFH 00007FFFH R 00000000H FFFFF000H FFFFC000H R 00000000H FFFFF000H FFFFE000H FFFF8000H FFFF8000H Internal ROM ar...

Page 74: ...ry On chip peripheral I O Internal RAM External memory External memory Internal ROM xxFFFFFFH xxFFF3C6H xxFFF3C5H xxFFF000H xxFFEFFFH xxFFC000H xxFFBFFFH xx100000H xx0FFFFFH xx040000H xx03FFFFH xx800000H xx7FFFFFH xx000000H FFFFF000H FFFFEFFFH FFFFC000H FFFFBFFFH FF800000H FF7FFFFFH 01000000H 00FFFFFFH 00FFF000H 00FFEFFFH 00FFC000H 00FFBFFFH 00800000H 007FFFFFH 00100000H 000FFFFFH 00020000H 0001FF...

Page 75: ...t 3 mode register PM3 FFFFF028H Port 4 mode register PM4 FFFFF02AH Port 5 mode register PM5 FFFFF02CH Port 6 mode register PM6 3FH FFFFF032H Port 9 mode register PM9 7FH FFFFF034H Port 10 mode register PM10 FFH FFFFF036H Port 11 mode register PM11 1FH FFFFF038H Port 12 mode register PM12 01H FFFFF04CH Memory expansion mode register MM 00H FFFFF058H Port 12 mode control register PMC12 FFFFF060H Dat...

Page 76: ...IC0 FFFFF104H Interrupt control register PIC1 FFFFF106H Interrupt control register PIC2 FFFFF108H Interrupt control register PIC3 FFFFF10AH Interrupt control register PIC4 FFFFF10CH Interrupt control register PIC5 FFFFF10EH Interrupt control register PIC6 FFFFF110H Interrupt control register WTIIC FFFFF112H Interrupt control register TMIC00 FFFFF114H Interrupt control register TMIC01 FFFFF116H Int...

Page 77: ... count register 1 DBC1 FFFFF196H DMA channel control register 1 DCHC1 00H FFFFF1A0H DMA peripheral I O address register 2 DIOA2 Undefined FFFFF1A2H DMA internal RAM address register 2 DRA2 FFFFF1A4H DMA byte count register 2 DBC2 FFFFF1A6H DMA channel control register 2 DCHC2 00H FFFFF200H 16 bit timer register 0 TM0 R 0000H FFFFF202H 16 bit capture compare register 00 CR00 Note FFFFF204H 16 bit c...

Page 78: ...FF26CH 16 bit compare register 45 CR45 R W FFFFF270H 8 bit counter 5 TM5 R 00H FFFFF272H 8 bit compare register 5 CR50 R W FFFFF274H Timer clock selection register 5 TCL5 FFFFF276H 8 bit timer mode control register 5 TMC5 04H FFFFF2A0H Serial I O shift register 0 SIO0 00H FFFFF2A2H Serial operation mode register 0 CSIM0 FFFFF2A4H Serial clock selection register 0 CSIS0 FFFFF2B0H Serial I O shift r...

Page 79: ...IIC clock selection register Note IICCL0 R W FFFFF346H Slave address register Note SVA0 FFFFF348H IIC shift register Note IIC0 FFFFF360H Watch timer mode register WTM FFFFF380H Oscillation stable time selection register OSTS 04H FFFFF382H Watchdog timer clock selection register WDCS 00H FFFFF384H Watchdog timer mode register WDTM FFFFF3A0H Real time output buffer register L RTBL FFFFF3A2H Real tim...

Page 80: ...tion instruction SET1 CLR1 NOT1 instruction 5 Return the PSW NP bit to 0 interrupt disable canceled 6 Insert the NOP instructions 2 or 5 instructions 7 Enable DMA operation if required No special sequence is required when reading the specific registers Caution 1 If an interrupt request is accepted between the time PRCMD is issued 3 and the specific register write operation 4 that follows immediate...

Page 81: ...lation of STOP IDLE mode rX Value to be written to PSW rY Value to be written back to PSW rD Value to be set to PSC When saving the value of PSW the value of PSW prior to setting the NP bit must be transferred to the rY register Caution 2 The instructions 5 interrupt disable cancel 6 NOP instruction following the store instruction for the PSC register for setting the software STOP mode and IDLE mo...

Page 82: ...register is allocated with status flags showing the operating state of the entire system This register can be read written in 8 or 1 bit units After reset 00H R W Address FFFFF078H Symbol 7 6 5 4 3 2 1 0 SYS 0 0 0 PRERR 0 0 0 0 PRERR Detection of Protection Error 0 Protection error does not occur 1 Protection error occurs Operation conditions of PRERR flag are shown as follows a Set conditions PRE...

Page 83: ...g pins are used for interfacing to external devices External Bus Interface Function Corresponding Port pins Address data bus AD0 to AD7 Port 4 P40 to P47 Address data bus AD8 to AD15 Port 5 P50 to P57 Address bus A16 to A21 Port 6 P60 to P65 Read write control LBEN UBEN R W DSTB WRL WRH RD Port 9 P90 to P93 Address strobe ASTB Port 9 P94 Bus hold control HLDRQ HLDAK Port 9 P95 P96 External wait co...

Page 84: ... 0 0 0 0 BIC BIC Bus Interface Control 0 DSTB R W UBEN LBEN signal outputs 1 RD WRL WRH UBEN signal outputs 4 3 Bus Access 4 3 1 Number of access clocks The number of basic clocks necessary for accessing each resource is as follows Peripheral I O bus width Bus Cycle Type Internal ROM 32 bits Internal RAM 32 bits Peripheral I O 16 bits External Memory 16 bits Instruction fetch 1 3 Disabled 3 n Oper...

Page 85: ... data External data bus a Access to even address 0 7 0 7 8 15 Byte data External data bus b Access to odd address 2 Halfword access 16 bits In halfword access to external memory data is dealt with as it is because the data bus is fixed to 16 bits 0 0 15 15 Halfword data External data bus 3 Word access 32 bits In word access to external memory lower halfword is accessed first and then the upper hal...

Page 86: ...15 Block 14 Block 13 Block 12 Block 11 Block 10 Block 9 Block 8 Block 7 Block 6 Block 5 Block 4 Block 3 Block 2 Block 1 Block 0 Peripheral I O area Internal RAM area External memory area FFFFFFH F00000H EFFFFFH E00000H DFFFFFH D00000H CFFFFFH C00000H BFFFFFH B00000H AFFFFFH A00000H 9FFFFFH 900000H 8FFFFFH 800000H 7FFFFFH 700000H 6FFFFFH 600000H 5FFFFFH 500000H 4FFFFFH 400000H 3FFFFFH 300000H 2FFFF...

Page 87: ... 4 3 2 1 0 DWC Number of Wait States to be Inserted 0 0 0 0 1 1 1 0 2 1 1 3 n Blocks into Which Wait States Are Inserted 0 Blocks 0 1 1 Blocks 2 3 2 Blocks 4 5 3 Blocks 6 7 4 Blocks 8 9 5 Blocks 10 11 6 Blocks 12 13 7 Blocks 14 15 Block 0 is reserved for the internal ROM area It is not subject to programmable wait control regardless of the setting of DWC and is always accessed without wait states ...

Page 88: ...s fied the wait state may or may not be inserted in the next state 4 5 3 Relations between programmable wait and external wait A wait cycle is inserted as a result of an OR operation between the wait cycle specified by the set value of pro grammable wait and the wait cycle controlled by the WAIT pin In other words the number of wait cycles is deter mined by the programmable wait value or the lengt...

Page 89: ...ycle control register BCC This register can be read written in 16 bit units After reset AAAAH R W Address FFFFF062H Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BCC Idle State Insert Specification 0 Not inserted 1 Inserted n Blocks into Which Idle State Is Inserted 0 Blocks 0 1 1 Blocks 2 3 2 Blocks 4 5 3 Blocks 6 7 4 Blocks 8 9 5 Blocks 10 11 6 Blocks 12 13 7 Blocks 14 15 Block 0 is reserved for ...

Page 90: ...ating that the request for the bus is cleared these pins are driven again During bus hold period the internal operation continues until the next external memory access In the bus hold status the HLDAK pin becomes active low This feature can be used to design a system where two or more bus masters exist such as when multi processor configuration is used and when a DMA controller is connected Bus ho...

Page 91: ...t request pending 9 Start of bus cycle Nomal status Bus hold status Normal status 4 7 3 Operation in power save mode In the STOP or IDLE mode the system clock is stopped Consequently the bus hold status is not set even if the HLDRQ pin becomes active In the HALT mode the HLDAK pin immediately becomes active when the HLDRQ pin becomes active and the bus hold status is set When the HLDRQ pin becomes...

Page 92: ...ls Set these modes by using the BIC bit of the system control register SYC 1 Memory read 0 wait T1 T2 T3 CLKOUT input A16 to A21 output AD0 to AD15 input output Address Data Address ASTB output R W output DSTB RD output UBEN LBEN output WAIT input WRH WRL output H A1 to A15 output Address Remarks 1 indicates the sampling timing when the number of programmable waits is set to 0 2 The broken line in...

Page 93: ...D0 to AD15 input output Address Address ASTB output R W output DSTB RD output UBEN LBEN output WAIT input WRH WRL output T3 Data H A1 to A15 output Address Remarks 1 indicates the sampling timing when the number of programmable waits is set to 0 2 The broken line indicates the high impedance state ...

Page 94: ...ut AD0 to AD15 input output Address Address ASTB output R W output UBEN LBEN output WAIT input DSTB RD output H TI Data WRH WRL output A16 to A21 output Address Remarks 1 indicates the sampling timing when the number of programmable waits is set to 0 2 The broken line indicates the high impedance state ...

Page 95: ...t AD0 to AD15 input output Address Address ASTB output R W output DSTB RD output UBEN LBEN output WAIT input WRH WRL output T3 Data TI H A16 to A21 output Address Remarks 1 indicates the sampling timing when the number of programmable waits is set to 0 2 The broken line indicates the high impedance state ...

Page 96: ...output UBEN LBEN output WAIT input RD output WRH WRL output H A1 to A15 output Address Note AD0 to AD7 output invalid data when odd address byte data is accessed AD8 to AD15 output invalid data when even address byte data is accessed Remarks 1 indicates the sampling timing when the number of programmable waits is set to 0 2 The broken line indicates the high impedance state ...

Page 97: ...tput WAIT input RD output WRH WRL output T3 DataNote Address H A1 to A15 output Address Note AD0 to AD7 output invalid data when odd address byte data is accessed AD8 to AD15 output invalid data when even address byte data is accessed Remarks 1 indicates the sampling timing when the number of programmable waits is set to 0 2 The broken line indicates the high impedance state ...

Page 98: ...Address ASTB output Undefined Address Note1 Note2 Notes 1 If HLDRQ signal is inactive high level at the sampling timing bus hold state is not entered 2 If transmitted to bus hold status after write cycle high level may be output momentarily from R W pin immediately before HLDAK signal transmits from high level to low level Remarks 1 indicates the sampling timing when the number of programmable wai...

Page 99: ...10 Memory Boundary Operation Condition 4 10 1 Program space 1 Do not execute branch to the on chip peripheral I O area or continuous fetch from the internal RAM area to pe ripheral I O area Of course it is impossible to fetch from external memory If branch or instruction fetch is exe cuted nevertheless the NOP instruction code is continuously fetched 2 A prefetch operation straddling over the on c...

Page 100: ...100 MEMO ...

Page 101: ...hardware and external sources Moreover exception processing can be started by the TRAP instruction software exception or by generation of an exception event fetching of an illegal op code 5 1 Features Interrupt Non maskable interrupt 2 sources Maskable interrupt 30 sources 8 levels programmable priorities Mask specification for the interrupt request according to priority Mask can be specified to e...

Page 102: ... 6 INTP5 INTP5 pin Pin 00E0H 000000E0H nextPC PIC5 7 INTP6 INTP6 pin Pin 00F0H 000000F0H nextPC PIC6 8 INTWTI Watch timer prescaler WT 0100H 00000100H nextPC WTIIC 9 INTTM00 INTTM00 TM0 0110H 00000110H nextPC TMIC00 10 INTTM01 INTTM01 TM0 0120H 00000120H nextPC TMIC01 11 INTTM10 INTTM10 TM1 0130H 00000130H nextPC TMIC10 12 INTTM11 INTTM11 TM1 0140H 00000140H nextPC TMIC11 13 INTTM2 TM2 compare coi...

Page 103: ...250H nextPC WTIC Notes 1 n value of 0 to FH 2 Valid only for the µPD703015Y and 70F3017Y Remarks 1 Default Priority Priority that takes precedence when two or more maskable interrupt requests occur at the same time The highest priority is 0 Restored PC The value of the PC saved to EIPC or FEPC when interrupt exception process ing is started However the value of the PC saved when an interrupt is gr...

Page 104: ... functions as the non maskable interrupt INTWDT only in the state which the WDTM4 bit of the watch dog timer mode register WDTM is set to 1 While the service routine of the non maskable interrupt is being executed PSW NP 1 the acceptance of an other non maskable interrupt request is kept pending The pending NMI is accepted after the original service routine of the non maskable interrupt under exec...

Page 105: ...rites exception code 0010H to the higher half word FECC of ECR 4 Sets the NP and ID bits of PSW and clears the EP bit 5 Loads the handler address 00000010H of the non maskable interrupt routine to the PC and transfers control Figure 5 1 Non Maskable Interrupt Processing NMI input Non maskable interrupt request Interrupt processing Interrupt request pending FEPC FEPSW ECR FECC PSW NP PSW EP PSW ID ...

Page 106: ...uest PSW NP 1 NMI request pending because PSW NP 1 Pending NMI request processed b If a new NMI request is generated twice while an NMI service routine is executing Main routine NMI request NMI request Kept pending because NMI service program is being processed Kept pending because NMI service program is being processed NMI request Only one NMI request is accepted even though two or more NMI reque...

Page 107: ...Transfers control back to the address of the restored PC and PSW Figure 5 3 illustrates how the RETI instruction is processed Figure 5 3 RETI Instruction Processing PSW EP RETI instruction PC PSW EIPC EIPSW PSW NP Original processing restored PC PSW FEPC FEPSW 1 1 0 0 Caution When the PSW EP bit and PSW NP bit are changed by the LDSR instruction during the non maskable interrupt process in order t...

Page 108: ...eset 00000020H Symbol 31 8 7 6 5 4 3 2 1 0 PSW 0 NP EP ID SAT CY OV S Z NP NMI Processing State 0 No NMI interrupt processing 1 NMI interrupt currently processing 5 2 4 Noise elimination circuit of NMI pin NMI pin noise is eliminated with analog delay The signal input that changes within a certain interval is not inter nally acknowledged NMI pin is used for canceling the software stop mode In the ...

Page 109: ...EGP0 EGP07 EGP06 EPG05 EPG04 EPG03 EPG02 EGP01 EGP00 EGP0n Rising Edge Valid Control 0 No interrupt request signal occurs at the rising edge 1 Interrupt request signal occurs at the rising edge n 0 NMI pin control n 1 to 7 INTP0 to INTP6 pins control Figure 5 5 Falling Edge Specification Register EGN0 Format After reset 00H R W Address FFFFF0C2H Symbol 7 6 5 4 3 2 1 0 EGN0 EGN07 EGN06 EGN05 EGN04 ...

Page 110: ...y level cannot be nested To use multiple interrupts it is necessary to save EIPC and EIPSW to memory or a register before executing the EI instruction and restore EIPC and EIPSW to the original values by executing the DI instruction before the RETI instruction The WDTM4 bit of the watchdog timer mode register WDTM is set to 0 and the watchdog timer overflow inter rupt functions as a maskable inter...

Page 111: ...t Yes Yes Yes Yes Priority higher than that of other interrupt request Highest default priority of interrupt requests with the same priority Interrupt enable mode restored PC PSW exception code 0 1 handler address The INT input masked by the interrupt controllers and the INT input that occurs while the other interrupt is being processed when PSW NP 1 or PSW ID 1 are internally pended by the interr...

Page 112: ...s control to the address of the restored PC and PSW Figure 5 7 illustrates the processing of the RETI instruction Figure 5 7 RETI Instruction Processing RETI instruction Restores original processing PC PSW EIPC EIPSW PSW EP 1 0 1 0 PC PSW FEPC FEPSW PSW NP Caution When the PSW EP bit and the PSW NP bit are changed by the LDSR instruction during the mas kable interrupt process in order to restore t...

Page 113: ... interrupts having the same priority level specified by xxPRn are generated at the same time interrupts are serviced in order depending on the priority level allocated to each interrupt request types default priority level be forehand For more information refer to Table 5 1 The programmable priority control customizes interrupt requests into eight levels by setting the priority level specification...

Page 114: ...ending even if interrupts are enabled because its priority is the same as that of g Interrupt request f is kept pending even if interrupts are enabled because its priority is lower than that of e Interrupt request b is accepted because the priority of b is higher than that of a and interrupts are enabled Although the priority of interrupt request d is higher than that of c d is kept pending becaus...

Page 115: ...Processing of p Processing of q Processing of r EI If levels 3 to 0 are accepted Interrupt request j is kept pending because its priority is lower than that of i k that occurs after j is accepted because it has the higher priority Interrupt requests m and n are kept pending because processing of l is performed in the interrupt disabled status Pending interrupt requests are accepted after processin...

Page 116: ...equest a level 2 Interrupt request b level 1 Interrupt request c level 1 Processing of interrupt request b Processing of interrupt request c Processing of interrupt request a Interrupt request b and c are accepted first according to their priorities Because the priorities of b and c are the same b is accepted first because it has the higher default priority ...

Page 117: ...PRn1 xxPRn0 xxIFn Interrupt request flag Note 0 Interrupt request not issued 1 Interrupt request issued xxMKn Interrupt mask flag 0 Enables interrupt processing 1 Disables interrupt processing pending xxPRn2 xxPRn1 xxPRn0 Interrupt priority specification bit 0 0 0 Specifies level 0 highest 0 0 1 Specifies level 1 0 1 0 Specifies level 2 0 1 1 Specifies level 3 1 0 0 Specifies level 4 1 0 1 Specifi...

Page 118: ...K11 0 0 0 TMPR112 TMPR111 TMPR110 FFFFF11AH TMIC2 TMIF2 TMMK2 0 0 0 TMPR22 TMPR21 TMPR20 FFFFF11CH TMIC3 TMIF3 TMMK3 0 0 0 TMPR32 TMPR31 TMPR30 FFFFF11EH TMIC4 TMIF4 TMMK4 0 0 0 TMPR42 TMPR41 TMPR40 FFFFF120H TMIC5 TMIF5 TMMK5 0 0 0 TMPR52 TMPR51 TMPR50 FFFFF122H CSIC0 CSIF0 CSMK0 0 0 0 CSPR02 CSPR01 CSPR00 FFFFF124H SERIC0 SERIF0 SERMK0 0 0 0 SERPR02 SERPR01 SERPR00 FFFFF126H CSIC1 CSIF1 CSMK1 0 ...

Page 119: ...upt request with priority n not accepted 1 Interrupt request with priority n accepted Remark n 0 to 7 priority level 5 3 6 Maskable interrupt status flag The interrupt disable status flag ID of the PSW controls the enabling and disabling of maskable interrupt re quests As a status flag it also displays the current maskable interrupt acceptance condition After reset 00000020H Symbol 31 8 7 6 5 4 3 ...

Page 120: ...of the analog delay Unless an input level to each pin is maintained more than a certain interval the input pulse cannot be detected as an edge The edge is detected in a certain interval 2 Noise elimination of INTP4 to INTP6 pins INTP4 to INTP6 pins incorporate the digital noise elimination circuit If an input level of the INTP pin is detected with the sampling clock fxx and the same level is not d...

Page 121: ...alling edge specification register EGN0 controls the validity of a falling edge NMI and INTP0 to INTP6 pins after reset is set to neither rising nor falling edge detected Unless a valid edge is enabled by the EGP0 or EGN0 register an interrupt request is not acknowledged These pins normally function as a port When P00 is used as an output port set the NMI valid edge to neither rising nor falling e...

Page 122: ...sfers control to the handler routine 1 Saves the restored PC to EIPC 2 Saves the current PSW to EIPSW 3 Writes an exception code to the lower 16 bits EICC of ECR interrupt source 4 Sets the EP and ID bits of PSW 5 Loads the handler address 00000040H or 00000050H of the software exception routine in the PC and trans fers control Figure 5 13 illustrates how a software exception is processed Figure 5...

Page 123: ...fers control to the address of the restored PC and PSW Figure 5 14 illustrates the processing of the RETI instruction Figure 5 14 RETI Instruction Processing PSW EP RETI instruction PC PSW EIPC EIPSW PSW NP Original processing restored PC PSW FEPC FEPSW 1 1 0 0 Caution When the PSW EP bit and the PSW NP bit are changed by the LDSR instruction during the soft ware exception process in order to rest...

Page 124: ... trap Illegal op code exception occurs if the subop code field of an instruction to be executed next is not a valid op code 5 5 1 Illegal op code definition An illegal op code is defined to be a 32 bit word with bits 5 to 10 being 111111B and bits 23 to 26 being 0011B to 1111B 15 16 17 2322 x 21 x 20 x x x x x x x x x x x x x x x 1 1 1 1 1 1 x x x x x 27 26 31 0 4 5 10 11 12 13 1 1 1 1 0 to 1 0 1 ...

Page 125: ...n processing 5 5 3 Restore To restore or return execution from the exception trap the RETI instruction is used Operation of RETI instruction When the RETI instruction is executed the CPU performs the following processing and transfers control to the address of the restored PC 1 Restores the restored PC and PSW from EIPC and EIPSW because the EP bit of PSW is 1 2 Transfers control to the address of...

Page 126: ...SW PSW NP Caution When the PSW EP bit and the PSW NP bit are changed by the LDSR instruction during the ex ception trap process in order to restore the PC and PSW correctly during recovery by the RETI instruction it is necessary to set PSW EP back to 1 using the LDSR instruction immediately be fore the RETI instruction Remark The solid line shows the CPU processing flow ...

Page 127: ... interrupts If a higher priority interrupt is generated and accepted it will be allowed to stop a current interrupt service routine in progress Execution of the original routine will resume once the higher priority interrupt routine is completed If an interrupt with a lower or equal priority is generated and a service routine is currently in progress the later in terrupt will be pended Multiple in...

Page 128: ...ister EI instruction enables interrupt acceptance DI instruction disables interrupt acceptance Restores saved value to EIPSW Restores saved value to EIPC RETI instruction Saves EIPC to memory or register Saves EIPSW to memory or register EI instruction enables interrupt acceptance TRAP instruction Illegal op code Restores saved value to EIPSW Restores saved value to EIPC RETI instruction Accepts i...

Page 129: ...he xxPRn0 to xxPRn2 bits Priorities of maskable interrupts High Level 0 Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Low Interrupt processing that has been suspended as a result of multiple interrupt processing is resumed after the in terrupt processing of the higher priority has been completed and the RETI instruction has been executed A pending interrupt request is accepted after the ...

Page 130: ...cknowledge processing IFx invalid instruction fetch IDx invalid instruction decode Interrupt Latency Time system clock Internal interrupt External interrupt Minimum 11 13 Maximum 18 20 5 8 Periods Where Interrupt is Not Acknowledged An interrupt is acknowledged while an instruction is being executed However no interrupt will be acknowledged between interrupt non sample instruction and next instruc...

Page 131: ...OP instruction a oscillation stabilization time is set after the stop mode is canceled This oscillation stabilization time is set via the oscillation stabilization time select register OSTS The watchdog timer is used as the timer that counts the oscillation stabilization time 2 Subsystem clock oscillator This circuit has an oscillation frequency of 32 768 kHz Its oscillation is not stopped when th...

Page 132: ...tput changing the CPU clock CK2 to CK0 bits of PCC register is disabled 6 3 1 Control registers 1 Processor clock control register PCC This is a specific register It can be written to only when a specified combination of sequences is used refer to 3 4 9 Specific registers This register can be read written in 8 or 1 bit units Figure 6 1 Format of Processor Clock Control Register PCC 1 2 After reset...

Page 133: ...changing the FLMD bit The FLMD bit is valid only for the µ µ µ µPD70F3017 and 70F3017Y flash memory incorporated In the µ µ µ µPD703015 and 703015Y mask ROM incorporated the FLMD bit can be read written but the low power consumption mode low speed mode cannot be selected The setting FLMD 1 is valid only when the CPU clock is less than 5 MHz If the CPU clock is 5 MHz or higher runaway may occur If ...

Page 134: ... Specification of CLKOUT Pin s Operation 0 0 Output enabled 0 1 Setting prohibited 1 0 Setting prohibited 1 1 Output disabled when reset CESEL Selection of Resonator and External Clock 0 Connect resonator to X1 and X2 1 Connect external clock to X1 Note 1 IDLE IDLE Mode Setting 0 Normal mode 1 IDLE mode Note 2 STP STOP Mode Setting 0 Normal mode 1 STOP mode Note 3 Notes 1 When CESEL 1 the oscillat...

Page 135: ... above Setting prohibited Note The numerical value in parentheses is the value when fXX 17 MHz 6 4 Power Saving Functions 6 4 1 General This product provides the following power saving functions These modes can be combined and switched to suit the target application which enables effective implementation of low power systems 1 HALT mode When in this mode the clock s oscillator continues to operate...

Page 136: ...he CPU clock is set to operate using the sub clock and the PCC register s MCK bit is set to 1 to set low power consumption mode during which the entire system operates using only the sub clock When HALT mode has been set the CPU s operating clock is stopped so that power consumption can be reduced When IDLE mode has been set the CPU s operating clock and some peripheral functions DMAC and BCU are ...

Page 137: ...rating Stopped 8 bit timer TM2 Operating Stopped 8 bit timer TM3 Operating Stopped 8 bit timer TM4 Operating Operates when fxt is selected for count clock 8 bit timer TM5 Operating Operates when fxt is selected for count clock Watch timer Operates when fxx 29 is selected for count clock Operating Operates when fxt is selected for count clock Watchdog timer Operating interval timer only Serial inte...

Page 138: ...ding to the status shown in the Table 6 1 2 Cancellation of HALT mode HALT mode can be canceled by an NMI request an unmasked maskable interrupt request and input to the RESET pin a Cancellation by interrupt request HALT mode is canceled regardless of the priority level when an NMI request or an unmasked maskable interrupt request occurs However the following occurs if HALT mode was set as part of...

Page 139: ...sted in Table 6 2 Table 6 2 Operating Statuses during IDLE Mode 1 2 Mode When Sub Clock Exists When Sub Clock Does Not Exist CPU Stopped Clock oscillator Oscillation for main clock and sub clock Clock supply to CPU and on chip peripheral functions is stopped 16 bit timer TM0 Operates when INTWTI is selected as count clock fxt is selected for watch timer Stopped 16 bit timer TM1 Stopped 8 bit timer...

Page 140: ... Stopped AD0 AD15 High impedance A16 A21 LBEN UBEN R W DSTB WRL WRH RD ASTB HLDAK 2 Cancellation of IDLE mode IDLE mode can be canceled by input to the NMI pin by an unmasked external interrupt request INTP0 to INTP3 by an unmasked interrupt request output from an on chip peripheral I O that can be operated or by input to the RESET pin External interrupt request During external expansion mode ...

Page 141: ...TP bit in the power saving control register PSC has been set to 1 Do not set this mode when the sub clock has been selected as the CPU clock The operating states for software STOP mode are listed in Table 6 3 Table 6 3 Operating States during Software STOP Mode 1 2 Mode Settings Item When Sub Clock Exists When Sub Clock Does Not Exist CPU Stopped Clock oscillator Oscillation for main clock is stop...

Page 142: ...er saving control register PSC has been cleared to 0 an oscillation stabilization time is required 6 5 Oscillation Stabilization Time The following shows methods for specifying the amount of oscillation stabilization time required to stabilize the oscillator following cancellation of STOP mode 1 Use of NMI pin and external interrupt request pin INTP0 to INTP3 to allocate time STOP mode is canceled...

Page 143: ...ode is set Interrupt input STOP status Main clock Oscillation ware Oscillator is stopped Count time value of time base counter 2 Use of RESET pin to allocate time RESET pin input For allocating time with RESET pin refer to CHAPTER 15 RESET FUNCTION ...

Page 144: ...144 MEMO ...

Page 145: ...red with TIn0 via digital noise rejection circuit and possible for edge specification Timer output operated by match detection 1 each TO0 TO1 When used for timer output TOn pin set port value to 0 port mode output ORed value of the output of a port and timer is output 7 1 2 Function TM0 and TM1 have the following functions Interval timer PPG output Pulse width measurement External event counter Sq...

Page 146: ...pulses of a signal input from an external source Internal bus Internal bus TIn1 Noise rejection circuit Noise rejection circuit Noise rejection circuit Prescaler mode register n PRMn Count clock Note TIn0 TOEn TOCn1 LVRn LVSn TOCn4 OSPEn OSPTn OVFn TMCn1 TMCn2 PRMn1 PRMn0 TMCn3 CRCn0 CRCn1 CRCn2 Capture compare control register n CRCn 16 bit capture compare register n0 CRn0 Output control circuit ...

Page 147: ...r 0 1 TOC0 TOC1 Prescaler mode register 0 1 PRM0 PRM1 1 16 bit timer register 0 1 TM0 TM1 TMn is a 16 bit read only register that counts count pulses The counter is incremented in synchronization with the rising edge of an input clock If the count value is read during operation input of the count clock is temporarily stopped and the count value at that point is read The count value is reset to 000...

Page 148: ...dge for TIn1 pin is specified as the capture trigger refer to Table 7 3 Table 7 2 Valid Edge of TIn0 Pin and Capture Trigger of CRn0 ESn01 ESn00 Valid Edge of TIn0 Pin CRn0 Capture Trigger 0 0 Falling edge Rising edge 0 1 Rising edge Falling edge 1 0 Setting prohibited Setting prohibited 1 1 Both rising and falling edges No capture operation Remark n 0 1 Table 7 3 Valid Edge of TIn1 Pin and Captur...

Page 149: ...e an interrupt request INTTMn1 is generated b When using CRn1 as capture register The valid edge of the TIn0 pin can be selected as a capture trigger The valid edge of TIn0 is specified by using the PRMn register CRn1 is set by using a 16 bit memory manipulation instruction The value of this register is undefined when the RESET signal is input Caution Set CRn1 to a value other than 0000H 1 pulse c...

Page 150: ... 1 16 bit timer mode control register 0 1 TMC0 TMC1 This register specifies the operation mode of the 16 bit timer and the clear mode output timing and overflow detection of the 16 bit timer register n TMCn is set by a 1 bit or 8 bit memory manipulation instruction RESET input clears TMC0 and TMC1 to 00H Caution The 16 bit timer register n starts operating when TMCn2 and TMCn3 are set to the value...

Page 151: ...nd CRn0 or coincidence between TMn and CRn1 0 1 1 Coincidence between TMn and CRn0 coincidence between TMn and CRn1 or valid edge of TIn0 1 0 0 Clears and starts at valid edge of TIn0 Coincidence between TMn and CRn0 or coincidence between TMn and CRn1 1 0 1 Coincidence between TMn and CRn0 coincidence between TMn and CRn1 or valid edge of TIn0 1 1 0 Clears and starts on coincidence between TMn an...

Page 152: ...rformed after halting the timer operation 2 The valid edge of the TIn0 pin is selected by using the prescaler mode register n PRMn 3 When a mode in which the timer is cleared and started on coincidence between TMn and CRn0 the OVFn flag is set to 1 when the count value of TMn changes from FFFFH to 0000H with CRn0 set to FFFFH Remark TOn Output pin of timer n TIn0 Input pin of timer n TMn 16 bit ti...

Page 153: ...ode of CRn1 0 Operates as compare register 1 Operates as capture register CRCn1 Selects Capture Trigger of CRn0 0 Captured at valid edge of TIn1 1 Captured in reverse phase of valid edge of TIn0 CRCn0 Selects Operation Mode of CRn0 0 Operates as compare register 1 Operates as capture register Cautions 1 Before setting CRCn be sure to stop the timer operation 2 When the mode in which the timer is c...

Page 154: ...ing or resetting the R S flip flop LV0 enabling or disabling reverse output enabling or disabling output of timer n enabling or disabling one shot pulse output operation and selecting an output trigger for a one shot pulse by software TOCn is set by a 1 bit or 8 bit memory manipulation instruction RESET input clears TOC0 and TOC1 to 00H Figure 7 4 shows the format of TOCn ...

Page 155: ...output F F 1 Enables reverse timer output F F LVSn LVRn Sets Status of Timer Output F F of Timer 0 0 0 Not affected 0 1 Resets timer output F F 0 1 0 Sets timer output F F 1 1 1 Setting prohibited TOCn1 Controls Timer Output F F on Coincidence between CRn0 and TMn and TIn0 Valid Edge 0 Disables reverse timer output F F 1 Enables reverse timer output F F TOEn Controls Output of Timer n 0 Disables o...

Page 156: ...1 0 Setting prohibited 1 1 Both rising and falling edges PRM01 PRM00 Selects Count Clock 0 0 fxx 2 8 5 MHz at fxx 17 MHz 0 1 fxx 16 1 06 MHz at fxx 17 MHz 1 0 Watch timer output INTWTI 1 1 Valid edge of TI00 Cautions 1 When selecting the valid edge of TI0n as the count clock do not specify the valid edge of TI0n to clear and start the timer and as a capture trigger 2 Set PRM0n after halting the ti...

Page 157: ...0 Setting prohibited 1 1 Both rising and falling edges PRM11 PRM10 Selects Count Clock 0 0 fxx 2 8 5 MHz at fxx 17 MHz 0 1 fxx 4 4 25 MHz at fxx 17 MHz 1 0 fxx 16 1 06 MHz at fxx 17 MHz 1 1 Valid edge of TI10 Cautions 1 When selecting the valid edge of TI1n as the count clock do not specify the valid edge of TI1n to clear and start the timer and as a capture trigger 2 Set PRM1n after halting the t...

Page 158: ...to 0 and the timer continues counting At the same time an interrupt request signal INTTMn0 is generated The count clock of the 16 bit timer event counter can be selected by bits 0 and 1 PRMn0 and PRMn1 of the prescaler mode register n PRMn Figure 7 7 Control Register Settings When Timer 0 Operates as Interval Timer a 16 bit timer mode control register 0 1 TMC0 TMC1 TMCn3 TMCn2 TMCn1 OVFn TMCn 0 0 ...

Page 159: ...Timing of Interval Timer Operation 0001H 0000H N N Interrupt accepted Interrupt accepted t TMn count value CRn0 0001H 0000H N 0001H 0000H N N INTTMn0 TOn Count clock N N Interval time Interval time Interval time Clear Count starts Clear Remarks 1 Interval time N 1 t N 0000H to FFFFH 2 n 0 1 16 bit capture compare register n0 CRn0 Count clock Note TIn0 Selector 16 bit timer register n TMn OVFn Clea...

Page 160: ...de control register 0 1 TMC0 TMC1 TMCn3 TMCn2 TMCn1 OVFn TMCn 0 0 0 0 1 1 0 0 Clears and starts on coincidence between TMn and CRn0 b Capture compare control register 0 1 CRC0 CRC1 CRCn2 CRCn1 CRCn0 CRCn 0 0 0 0 0 0 0 CRn0 as compare register CRn1 as compare register c 16 bit timer output control register 0 1 TOC0 TOC1 OSPTn OSPEn TOCn4 LVSn LVRn TOCn1 TOEn TOCn 0 0 0 1 0 1 0 1 1 1 Enables TOn out...

Page 161: ...y using bits 6 and 7 ESn10 and ESn11 of the prescaler mode register n PRMn The rising edge falling edge or both the rising and falling edges can be selected The valid edge is detected through sampling at a count clock cycle selected by the prescaler mode register n PRMn and the capture operation is not performed until the valid level is detected two times Therefore noise with a short pulse width c...

Page 162: ...Figure 7 13 Timing of Pulse Width Measurement with Free Running Counter and One Capture Register with both edges specified D0 D1 D2 D3 D3 D2 0000H FFFFH D1 D0 0001H 0000H t OVFn INTTMn1 TIn0 pin input TMn count value Count clock Value loaded to CRn1 D0 1 D0 1 10000H D1 D2 t D3 D2 t D1 D0 t Remark n 0 1 16 bit capture compare register n1 CRn1 16 bit timer register n TMn Internal bus Count clock Not...

Page 163: ... specified by bits 4 and 5 ESn00 and ESn01 and bits 6 and 7 ESn10 and ESn11 of PRMn respectively The rising falling or both rising and falling edges can be specified The valid edge is detected through sampling at a count clock cycle selected by the prescaler mode register n PRMn and the capture operation is not performed until the valid level is detected two times Therefore noise with a short puls...

Page 164: ...emark n 0 1 Figure 7 16 Timing of Pulse Width Measurement with Free Running Counter with both edges specified Value loaded to CRn1 D3 D2 t Count clock TMn count value TIn0 pin input INTTMn1 TIn1 pin input INTTMn0 OVFn Value loaded to CRn0 D3 0000H FFFFH D1 D0 0001H 0000H D0 D1 D1 t D0 1 D1 1 D1 D0 t 10000H D1 D2 1 t D2 1 D2 D2 D2 2 D2 1 10000H D1 D2 t Remark n 0 1 Rising edge detection Count clock...

Page 165: ...alid edge of TIn0 is detected through sampling at a count clock cycle selected by the prescaler mode register n PRMn and the capture operation is not performed until the valid level is detected two times Therefore noise with a short pulse width can be rejected Caution If the valid edge of the TIn0 pin is specified to be both the rising and falling edges the capture compare register n0 CRn0 cannot ...

Page 166: ... can be measured by clearing the 16 bit timer register n TMn once and then resuming counting after loading the count value of TMn to the 16 bit capture compare register n1 CRn1 The edge is specified by bits 4 and 5 ESn00 and ESn01 of prescaler mode register n PRMn The rising or falling edge can be specified The valid edge is detected through sampling at a count clock cycle selected by the PRMn and...

Page 167: ... 1 1 CRn0 as capture register Captures to CRn0 at edge reverse to valid edge of TIn0 CRn1 as capture register Remark 0 1 When these bits are reset to 0 or set to 1 the other functions can be used along with the pulse width measurement function For details refer to Figures 7 2 and 7 3 Figure 7 20 Timing of Pulse Width Measurement by Restarting with rising edge specified D1 t D2 t Count clock TMn co...

Page 168: ...gister n PRMn The rising falling or both the rising and falling edges can be specified The valid edge is detected through sampling at a count clock cycle of fxx and the capture operation is not performed until the valid level is detected two times Therefore noise with a short pulse width can be rejected Figure 7 21 Control Register Settings in External Event Counter Mode a 16 bit timer mode contro...

Page 169: ... 7 2 5 Operation to output square wave Timer 0 can be used to output a square wave with any frequency at an interval specified by the count value set in advance to the 16 bit capture compare register n0 CRn0 By setting bits 0 TOEn and 1 TOCn1 of the 16 bit timer output control register n TOCn to 1 the output status of the TOn0 pin is reversed at an interval specified by the count value set in adva...

Page 170: ... 0 0 1 0 1 1 CRn0 as compare register c 16 bit timer output control register 0 1 TOC0 TOC1 OSPTn OSPEn TOCn4 LVSn LVRn TOCn1 TOEn TOCn 0 0 0 0 0 1 0 1 1 1 Enables TOn0 output Reverses output on coincidence between TMn and CRn0 Specifies initial value of TOn0 output F F Does not reverse output on coincidence between TMn and CRn1 Disables one shot pulse output Remark 0 1 When these bits are reset to...

Page 171: ...ister n CRCn and 16 bit timer output control register n TOCn as shown in Figure 7 26 and by setting bit 6 OSPTn of TOCn by software By setting OSPTn to 1 the 16 bit timer event counter is cleared and started and its output is asserted active at the count value set in advance to the 16 bit capture compare register n1 CRn1 After that the output is deasserted inactive at the count value set in advanc...

Page 172: ... CRn0 as compare register CRn1 as compare register c 16 bit timer output control register 0 1 TOC0 TOC1 OSPTn OSPEn TOCn4 LVSn LVRn TOCn1 TOEn TOCn 0 0 1 1 0 1 0 1 1 1 Enables TOn0 output Reverses output on coincidence between TMn and CRn0 Specifies initial value of TOn0 output F F Reverses output on coincidence between TMn and CRn1 Sets one shot pulse output mode Set to 1 for output Remark 0 1 Wh...

Page 173: ...capture compare control register n CRCn and 16 bit timer output control register n TOCn as shown in Figure 7 28 and by using the valid edge of the TIn0 pin as an external trigger The valid edge of the TIn0 pin is specified by bits 4 and 5 ESn00 and ESn01 of the prescaler mode register n PRMn The rising falling or both the rising and falling edges can be specified When the valid edge of the TIn0 pi...

Page 174: ...mpare register c 16 bit timer output control register 0 1 TOC0 TOC1 OSPTn OSPEn TOCn4 LVSn LVRn TOCn1 TOEn TOCn 0 0 1 1 0 1 0 1 1 1 Enables TOn0 output Reverses output on coincidence between TMn and CRn0 Specifies initial value of TOn0 output F F Reverses output on coincidence between TMn and CRn1 Sets one shot pulse output mode Caution Set a value in the following range to CRn0 and CRn1 0000H CRn...

Page 175: ...H Caution The 16 bit timer register starts operating as soon as a value other than 0 0 operation stop mode has been set to TMCn2 and TMCn3 Remark n 0 1 7 2 7 Cautions 1 Error on starting timer An error of up to 1 clock occurs before the coincidence signal is generated after the timer has been started This is because the 16 bit timer register n TMn is started asynchronously in respect to the count ...

Page 176: ...ter Changing Compare Register during Timer Count Operation TMn count value Count pulse 0002H 0001H 0000H FFFFH X X 1 N CRn0 M Remarks 1 N X M 2 n 0 1 3 Data hold timing of capture register If the valid edge is input to the TIn0 pin while the 16 bit capture compare register n1 CRn1 is read CRn1 performs the capture operation but this capture value is not guaranteed However the interrupt request fla...

Page 177: ...se is output do not set OSPTn to 1 Do not output the one shot pulse again until INTTMn0 which occurs on coincidence between TMn and CRn0 occurs b One shot pulse output with external trigger If the external trigger occurs while a one shot pulse is output it is ignored 6 Operation of OVFn flag The OVFn flag is set to 1 in the following case Select mode in which timer 0 is cleared and started on coin...

Page 178: ...l mode The timer operates as an 8 bit timer event counter It can have the following functions Interval timer External event counter Square wave output PWM output 2 Mode using the cascade connection 16 bit resolution cascade connection mode The timer operates as a 16 bit timer event counter by connecting TM2 and TM3 or TM4 and TM5 in cascade It can have the following functions Interval timer with 1...

Page 179: ...e Set by TCLn register Remarks 1 is a signal that can be directly connected to the port 2 n 2 to 5 7 3 2 Configuration Timer n is constructed from the following hardware Table 7 4 Timer 2 5 Configuration Item Configuration Timer register 8 bit counter 2 to 5 TM2 to TM5 16 bit counter 23 45 TM23 TM45 Only when connecting in cascade Register 8 bit compare register 2 to 5 CR20 CR30 CR40 CR50 16 bit c...

Page 180: ...0H 1 RESET is input 2 TCEn is cleared 3 TMn and CRn0 match in the clear and start mode Caution The cascade connection time becomes 00H even when TCEn in the lowest order timer is cleared 2 8 bit compare register 2 5 CR20 CR50 The value set in CRn0 is always compared to the count in the 8 bit counter n TMn If the two values match an interrupt request INTTMn is generated except in the PWM mode The v...

Page 181: ...ster 2 and 3 TCL2 TCL3 After reset 00H R W Address FFFFF244H FFFFF254H 7 6 5 4 3 2 1 0 TCLn 0 0 0 0 0 TCLn2 TCLn1 TCLn0 n 2 3 TCLn2 TCLn1 TCLn0 Count Clock Selection 0 0 0 Falling edge of TIn 0 0 1 Rising edge of TIn 0 1 0 fxx 4 4 25 MHz 0 1 1 fxx 8 2 13 MHz 1 0 0 fxx 16 1 06 MHz 1 0 1 fxx 32 531 kHz 1 1 0 fxx 128 133 kHz 1 1 1 fxx 512 33 2 kHz Cautions 1 When TCLn is overwritten by different data...

Page 182: ...et bits 3 to 7 to 0 Remarks 1 Parenthesized values are applied when fxx 17 MHz 2 When connected in cascade the settings of TCLn2 to TCLn0 except for the lowest order timer are disabled 2 8 bit timer mode control register 2 5 TMC2 TMC5 The TMCn register makes the following six settings 1 Controls the counting by the 8 bit counter n TMn 2 Selects the operating mode of the 8 bit counter n TMn 3 Selec...

Page 183: ...tion 0 Clear and start mode when TMn and CRn0 match 1 PWM free running mode TMCn4 Individual Mode or Cascade Connection Mode Selection 0 Individual mode used by the lowest order timer fixed to 0 when n 2 4 1 Cascade connection mode connection with low order timer LVSn LVRn Setting the State of the Timer Output Flip Flop 0 0 No change 0 1 Reset the timer output flip flop to 0 1 0 Set the timer outp...

Page 184: ...ble output Cautions 1 When using as the timer output TOn pin set the port value to 0 port mode output An ORed value of the timer output value is output 2 Since the TOn pin and TIn pin are alternate pin either function can only be used Remarks 1 In the PWM mode the PWM output is set to the inactive level by TCEn 0 2 If LVSn and LVRn are read after setting data 0 is read ...

Page 185: ...k selection register n TCLn Setting method 1 Set each register TCLn Selects the count clock CRn0 Compare value TMCn Selects the clear and start mode when TMn and CRn0 match TMCn 0000xxx0B x is don t care 2 When TCEn 1 is set counting starts 3 When the values of TMn and CRn0 match INTTMn is generated TMn is cleared to 00H 4 Then INTTMn is repeatedly generated during the same interval When counting ...

Page 186: ...peration 2 3 When CRn0 00H Count clock CRn0 TCEn INTTMn TOn TMn 00H 00H 00H 00H 00H Interval time t Remark n 2 to 5 When CRn0 FFH Interrupt received 00H FFH FEH 01H FFH FFH FFH Count clock TMn CRn0 TCEn INTTMn TOn Interrupt received Interval time t 00H FFH FEH Remark n 2 to 5 ...

Page 187: ...Remark n 2 to 5 7 4 2 Operating as external event counter The external event counter counts the number of external clock pulses that are input to TIn Each time a valid edge specified in the timer clock selection register n TCLn is input TMn is incremented The edge setting can be selected to be either a rising or falling edge If the total of TMn and the value of the 8 bit compare register n CRn0 ma...

Page 188: ... CRn0 as the interval Therefore a square wave output having any frequency duty cycle 50 is possible Setting method 1 Set the registers Set the port latch and port mode register to 0 TCLn Select the count clock CRn0 Compare value TMCn Clear and start mode when TMn and CRn0 match LVSn LVRn Setting State of Timer Output Flip flop 1 0 High level output 0 1 Low level output Inversion of timer output fl...

Page 189: ... the PWM output Setting method 1 Set the port latch and port mode register n to 0 2 Set the active level width in the 8 bit compare register n CRn0 3 Select the count clock in the timer clock selection register n TCLn 4 Set the active level in bit 1 TMCn1 of TMCn 5 If bit 7 TCEn of TMCn is set to 1 counting starts When counting stops set TCEn to 0 PWM output operation 1 When counting starts the PW...

Page 190: ...Mn CRn0 TCEn INTTMn TOn Active level Active level Inactive level When CRn0 0 Count clock 00H 01H FFH 00H 01H 02H N N 1 00H TMn CRn0 TCEn INTTMn TOn FFH 00H 01H 02H M Inactive level N 2 00H Inactive level When CRn0 FFH FFH TMn CRn0 TCEn INTTMn TOn Inactive level Active level Active level 00H 01H FFH 00H 01H 02H Inactive level Inactive level Count clock N N 1 FFH 00H 01H 02H M N 2 00H Remark n 2 to ...

Page 191: ...N 2 01H M 1 M 2 N M CRn0 transition N M H When the CRn0 value changes from N to M after TMn overflows TCEn TMn CRn0 INTTMn TOn Count clock N 1 FFH 00H 01H 02H N 2 M M 1 M 2 FFH 03H 02H 01H 00H N N N 1 N M CRn0 transition N M H N N 2 When the CRn0 value changes from N to M during two clocks 00H 01H immediately after TMn overflows INTTMn TMn CRn0 TCEn TOn Count clock 02H 01H 00H FFH N 1 N 02H 01H 00...

Page 192: ...gh order timers connected in cascade are not used in setting CRn0 Compare values Each compare value can be set from 00H to FFH TMCn Select the clear and start mode when TMn and CRn0 match Lowest order timer TMCn 0000xxx0B x don t care Other timer TMCn 0001xxx0B x don t care 2 Setting TCEn 1 for the high order timer and finally setting TCEn 1 in the low order timer starts the count operation 3 If t...

Page 193: ...re 7 42 Cascade Connection Mode with 16 Bit Resolution A 00H B 00H Operation stopped Count clock TCEn INTTMn TCEn 1 Enable operation Starting count 00H N N 1 01H N M FFH 00H FFH 00H 01H FFH 00H N 00H 01H 00H TOn TMn 1 CRn0 TMn CR n 1 0 01H 02H M 1 M 00H Interrupt generated Level inverted Counter cleared Interval time Remark n 2 4 ...

Page 194: ...ister TMn counting continues overflows and counting starts again from 0 Consequently when the value M after CRn0 changes is less than the value N before the change the timer must restart after CRn0 changes Figure 7 44 Timing After Compare Register Changes During Timer Counting N M Count pulse CRn0 X X 1 FFH 00H 01H 02H TMn count value Remarks 1 N X M 2 n 2 to 5 Caution Except when the TIn input is...

Page 195: ...ions can be used at the same time Figure 8 1 shows the block diagram of the watch timer Figure 8 1 Block Diagram of Watch Timer fw 2 9 9 bit prescaler fw fw 2 8 fw 2 7 fw 2 6 fw 2 5 fw 2 4 5 bit counter INTWT INTWTI WTM7 WTM0 WTM1 WTM3 WTM4 WTM5 WTM6 Watch timer mode control register WTM Selector fxx 2 9 fxt Internal bus Clear Clear Selector Selector ...

Page 196: ...tervals specified in advance Table 8 1 Interval Time of Interval Timer Interval Time fW 32 768 kHz 2 4 1 fW 488 µs 2 5 1 fW 977 µs 2 6 1 fW 1 95 ms 2 7 1 fW 3 91 ms 2 8 1 fW 7 81 ms 2 9 1 fW 15 6 ms Remark fw Frequency for watch timer clock 8 2 Configuration The watch timer consists of the following hardware Table 8 2 Configuration of Watch Timer Item Configuration Counter 5 bits 1 Prescaler 9 bit...

Page 197: ...instruction RESET input clears WTM to 00H Figure 8 2 Format of Watch Timer Mode Control Register WTM 1 2 After reset 00H R W Address FFFFF360H 7 6 5 4 3 2 1 0 WTM WTM7 WTM6 WTM5 WTM4 WTM3 0 WTM1 WTM0 WTM7 Selects Count Clock of Watch Timer 0 fxx 2 9 Main clock 1 fxt Subclock WTM6 WTM5 WTM4 Selects Interval Time of Prescaler 0 0 0 2 4 fW 488 µs 0 0 1 2 5 fW 977 µs 0 1 0 2 6 fW 1 95 ms 0 1 1 2 7 fW ...

Page 198: ...The watch timer generates an interrupt request at fixed time intervals The count operation of the watch timer is started when bits 0 WTM0 and 1 WTM1 of the watch timer mode control register WTM are set to 1 When these bits are cleared to 0 the 5 bit counter is cleared and the watch timer stops the count operation When the interval timer function is started at the same time the watch timer can be s...

Page 199: ...1 fW 964 µs 977 µs 0 1 0 2 6 1 fW 19 3 ms 1 95 ms 0 1 1 2 7 1 fW 38 6 ms 3 91 ms 1 0 0 2 8 1 fW 77 1 ms 7 81 ms 1 0 1 2 9 1 fW 59 4 ms 15 6 ms Others Setting prohibited Remark fXX Main clock oscillation frequency fXT Subclock oscillation frequency fW Watch timer clock frequency Figure 8 3 Operation Timing of Watch Timer Interval Timer Remark fW Watch timer clock frequency fW 32 768 kHz n Interval ...

Page 200: ...200 MEMO ...

Page 201: ...val timer mode Figure 9 1 is a block diagram of the watchdog timer Figure 9 1 Block Diagram of Watchdog Timer Frequency division mode selection circuit Internal bus fxx 3 RUN Frequency divider Frequency division clock selection circuit Clock input control circuit Output control circuit INTWDT Note1 INTWDTM Note2 WDT mode signal WDTM4 WDCS2 WDCS1 WDCS0 OSTS2 OSTS1 OSTS0 Notes 1 When watchdog timer ...

Page 202: ...ms 2 16 fxx 3 855 ms 2 17 fxx 7 710 ms 2 18 fxx 15 42 ms 2 19 fxx 30 84 ms 2 20 fxx 61 68 ms 2 22 fxx 246 7 ms Note Parenthesized values apply when fxx 17 MHz 2 Interval timer mode Interrupts are generated at a preset time interval Table 9 2 Interval Time Interval Time Note 2 14 fxx 964 µs 2 15 fxx 1 928 ms 2 16 fxx 3 855 ms 2 17 fxx 7 710 ms 2 18 fxx 15 42 ms 2 19 fxx 30 84 ms 2 20 fxx 61 68 ms 2...

Page 203: ...ster WDTM 1 Oscillation stabilization time selection register OSTS This register selects the oscillation stabilization time after a reset is applied or the STOP mode is released until the oscillation is stable OSTS is set by an 8 bit memory manipulation instruction RESET input sets OSTS to 04H Figure 9 2 Format of Oscillation Stabilization Time Selection Register OSTS After reset 04H R W Address F...

Page 204: ...re 9 3 Format of Watchdog Timer Clock Selection Register WDCS After reset 00H R W Address FFFFF382H 7 6 5 4 3 2 1 0 WDCS 0 0 0 0 0 WDCS2 WDCS1 WDCS0 WDCS2 WDCS1 WDCS0 Watchdog Timer Interval Timer Overflow Time Note 0 0 0 2 14 fxx 964 µs 0 0 1 2 15 fxx 1 928 ms 0 1 0 2 16 fxx 3 855 ms 0 1 1 2 17 fxx 7 710 ms 1 0 0 2 18 fxx 15 42 ms 1 0 1 2 19 fxx 30 84 ms 1 1 0 2 20 fxx 61 68 ms 1 1 1 2 22 fxx 246...

Page 205: ...Disable count 1 Clear count and start counting WDTM4 Operating Mode Selection for the Watchdog Timer Note2 0 Interval timer mode If an overflow occurs a maskable interrupt INTWDTM is generated 1 Watchdog timer mode 1 If an overflow occurs a nonmaskable interrupt INTWDT is generated Notes 1 If RUN is set once to 1 the register cannot be cleared to 0 by software Therefore when the count starts the c...

Page 206: ... and clear the watchdog timer before entering the STOP mode or IDLE mode However in the case of STOP mode clearing or holding the watchdog timer differs CESEL 0 clear CESEL 1 hold according to the value of CESEL bit of the power saving control register PSC Do not set the watchdog timer when operating the HALT mode since the watchdog timer running in HALT mode Cautions 1 Sometimes the actual runawa...

Page 207: ...to 1 and the interval timer is cleared before entering the STOP mode IDLE mode execute the STOP instruction However in the case of STOP mode clearing or holding the interval timer differs CESEL 0 clear CESEL 1 hold according to the value of CESEL bit of the power saving control register PSC Cautions 1 If bit 4 WDTM4 of WDTM is set to 1 once selecting the watchdog timer mode the interval timer mode...

Page 208: ...4H R W Address FFFFF380H 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Oscillation Stabilization Time Selection Note 0 0 0 2 14 fxx 964 µs 0 0 1 2 16 fxx 3 855 ms 0 1 0 2 17 fxx 7 710 ms 0 1 1 2 18 fxx 15 42 ms 1 0 0 2 19 fxx 30 84 ms Otherwise Setting prohibited Note Parenthesized values apply when fxx 17 MHz Caution The wait time at the release of the STOP mode does not incl...

Page 209: ...ng two modes Operation stop mode 3 wire serial I O mode 1 Operation stop mode This mode is used when serial transfers are not performed 2 3 wire serial I O mode fixed as MSB first This is an 8 bit data transfer mode using three lines a serial clock line SCKn serial output line SOn and serial input line SIn Since simultaneous transmit and receive operations are enabled in 3 wire serial I O mode the...

Page 210: ...n 0 2 1 Serial I O shift register 0 2 SIO0 SIO2 This is an 8 bit register that performs parallel serial conversion and serial transmit receive shift operations synchronized with the serial clock SIOn is set by an 8 bit memory manipulation instruction When 1 is set to bit 7 CSIEn of the serial operation mode register n CSIMn a serial operation can be started by writing data to or reading data from ...

Page 211: ...t serial interface channel n s serial clock CSISn can be set by a 1 bit or 8 bit memory manipulation instruction RESET input sets these registers to 00H Figure 10 2 Format of Serial Operation Mode Register 0 2 CSIM0 CSIM2 1 2 After reset 00H R W Address CSIM0 FFFFF2A2H CSIM1 FFFFF2B2H CSIM2 FFFFF2C2H 7 6 5 4 3 2 1 0 CSIMn CSIEn 0 0 0 0 MODEn SCLn1 SCLn0 n 0 2 SIOn Operation Enable Disable Specific...

Page 212: ... at n 0 TO2 at n 1 2 TO3 0 1 0 fxx 8 2 125 MHz 0 1 1 fxx 16 1 0626 MHz 1 1 0 fxx 32 531 3 kHz 1 1 1 fxx 64 265 6 kHz Others Setting prohibited Caution Do not perform bit manipulation of the SCLn1 and SCLn0 Remarks 1 Parenthesized values apply when fxx 17 MHz 2 Refer to Figure 10 3 for the SCLn2 bit Figure 10 3 Format of Serial Clock Selection Registers 0 2 CSIS0 CSIS2 After reset 00H R W Address C...

Page 213: ...by a 1 bit or 8 bit memory manipulation instruction RESET input sets the register to 00H Figure 10 4 Format of Serial Operation Mode Register 0 2 CSIM0 CSIM2 After reset 00H R W Address CSIM0 FFFFF2A2H CSIM1 FFFFF2B2H CSIM2 FFFFF2C2H 7 6 5 4 3 2 1 0 CSIMn CSIEn 0 0 0 0 MODEn SCLn1 SCLn0 n 0 2 SIOn Operation Enable Disable Specification Shift register operation Serial counter Port Note 0 Operation ...

Page 214: ...ode Registers 0 2 CSIM0 CSIM2 1 2 After reset 00H R W Address CSIM0 FFFFF2A2H CSIM1 FFFFF2B2H CSIM2 FFFFF2C2H 7 6 5 4 3 2 1 0 CSIMn CSIEn 0 0 0 0 MODEn SCLn1 SCLn0 n 0 2 SIOn Operation Enable Disable Specification Shift register operation Serial counter Port Note 0 Operation disable Clear Port function 1 Operation enable Count operation enable Serial function port function Note When CSIEn 1 SIOn o...

Page 215: ...ts Each bit of data is sent or received in synchronized with the serial clock The serial I O shift register n SIOn is shifted in synchronized with the falling edge of the serial clock Transmission data is held in the SOn latch and is output from the SOn pin Data that is received via the SIn pin in synchronized with the rising edge of the serial clock is latched to SIOn Completion of an 8 bit trans...

Page 216: ...sfer the internal serial clock is either stopped or is set to high level Transmit receive mode When CSIEn 1 and MODEn 0 transfer starts when writing to SIOn Receive only mode When CSIEn 1 and MODEn 1 transfer starts when reading from SIOn Caution After data has been written to SIOn transfer will not start even if the CSIEn bit value is set to 1 Completion of an 8 bit transfer automatically stops t...

Page 217: ...sed to reduce power consumption 2 I 2 C bus mode multi master support This mode is used for 8 bit data transfers with several devices via two lines a serial clock SCL line and a serial data bus SDA line This mode complies with the I 2 C bus format and can output start condition data and stop condition data segments when transmitting via the serial data bus These data segments are automatically det...

Page 218: ...L1 CL0 SDA SCL N ch open drain output Data hold time correction circuit ACK detection circuit Wake up control circuit ACK detection circuit Stop condition detection circuit Serial clock counter Interrupt request signal generator Serial clock control circuit Serial clock wait control circuit Prescaler INTIIC0 fxx TM2 output CLD IIC clock select register IICCL0 Internal bus LREL WREL SPIE WTIM ACKE ...

Page 219: ...configuration example Figure 10 8 Serial Bus Configuration Example Using I 2 C Bus SDA SCL SDA VDD VDD SCL SDA SCL Slave CPU3 Address 2 SDA SCL Slave IC Address 3 SDA SCL Slave IC Address N Master CPU1 Slave CPU1 Serial data bus Serial clock Master CPU2 Slave CPU2 Address 1 ...

Page 220: ... reception Write and read operations to IIC0 are used to control the actual transmit and receive operations IIC0 is set by an 8 bit memory manipulation instruction RESET input sets the IIC0 to 00H 2 Slave address register SVA0 This register sets local addresses when in slave mode SVA0 is set by an 8 bit memory manipulation instruction RESET input sets the SVA0 to 00H 3 SO latch The SO latch is use...

Page 221: ...equest generated when a stop condition is detected set by SPIE bit Note Note WTIM bit bit 3 of the IIC control register IICC0 SPIE bit bit 4 of the IIC control register IICC0 8 Serial clock control circuit During master mode this circuit generates the clock output via the SCL pin from a sampling clock 9 Serial clock wait control circuit This circuit controls the wait timing 10 ACK output circuit s...

Page 222: ...register IIC0 Slave address register SVA0 1 IIC control register IICC0 This register is used to enable disable I 2 C operations set wait timing and set other I 2 C operations IICC0 can be set by a 1 bit or 8 bit memory manipulation instruction RESET input sets IICC0 to 00H Caution In I 2 C bus mode set the port 1 mode register PM1 as follows where each output latch is set to 0 Set P10 SDA to the o...

Page 223: ...ally irrelevant extension code has been received The SCL and SDA lines are set for high impedance The following flags are cleared STD ACKD TRC COI EXC MSTS STT SPT The standby mode following exit from communications remains in effect until the following communications entry conditions are met After a stop condition is detected restart is in master mode An address match or extension code receptions...

Page 224: ...et Slave mode After input of eight clocks the clock is set to low level and wait is set for master device 1 Interrupt request is generated at the ninth clock s falling edge Master mode After output of nine clocks clock output is set to low level and wait is set Slave mode After input of nine clocks the clock is set to low level and wait is set for master device This bit s setting is invalid during...

Page 225: ...has elapsed SCL is changed to low level When bus is not used This trigger functions as a start condition reserve flag When set it releases the bus and then automatically generates a start condition Wait state in master mode Releases the wait and generates the start condition Cautions concerning set timing For master reception Cannot be set during transfer Can be set only when ACKE has been set to ...

Page 226: ...iod that follows output of eight clocks note that a stop condition will be generated during the high level period of the ninth clock When a ninth clock must be output WTIM should be changed from 0 to 1 during the wait period following output of eight clocks and SPT should be set during the wait period that follows output of the ninth clock Condition for clearing SPT 0 Note 2 Condition for setting ...

Page 227: ...etting MSTS 1 When a stop condition is detected When ALD 1 Cleared by LREL 1 When IICE changes from 1 to 0 When RESET is input When a start condition is generated ALD Detection of Arbitration Loss 0 This status means either that there was no arbitration or that the arbitration result was a win 1 This status indicates the arbitration result was a loss MSTS is cleared Condition for clearing ALD 0 Co...

Page 228: ... When RESET is input When the received address matches the local address SVA0 set at the rising edge of the eighth clock TRC Detection of Transmit Receive Status 0 Receive status other than transmit status The SDA line is set for high impedance 1 Transmit status The value in the SO latch is enabled for output to the SDA line valid starting at the falling edge of the first byte s ninth clock Condit...

Page 229: ...n effect Condition for clearing STD 0 Condition for setting STD 1 When a stop condition is detected At the rising edge of the next byte s first clock following address transfer Cleared by LREL 1 When IICE changes from 1 to 0 When RESET is input When a start condition is detected SPD Detection of Stop Condition 0 Stop condition was not detected 1 Stop condition was detected The master device s comm...

Page 230: ...evel valid only when IICE 1 0 SCL line was detected at low level 1 SCL line was detected at high level Condition for clearing CLD 0 Condition for setting CLD 1 When the SCL line is at low level When IICE 0 When RESET is input When the SCL line is at high level DAD Detection of SDA Line Level valid only when IICE 1 0 SDA line was detected at low level 1 SDA line was detected at high level Condition...

Page 231: ...Response time is slower when the digital filter is used Remark don t care 4 IIC shift register IIC0 This register is used for serial transmission reception shift operations that are synchronized with the serial clock It can be read from or written to in 8 bit units but data should not be written to IIC0 during a data transfer After reset 00H R W Address FFFFF348H 7 6 5 4 3 2 1 0 IIC0 5 Slave addre...

Page 232: ...s Input is Schmitt input SDA This pin is used for serial data input and output This pin is an N ch open drain output for both master and slave devices Input is Schmitt input Since outputs from the serial clock line and the serial data bus line are N ch open drain outputs an external pull up resistor is required Figure 10 12 Pin Configuration Diagram VDD SCL SDA SCL SDA VDD Clock output Master devi...

Page 233: ... condition slave address and stop condition The acknowledge signal ACK can be output by either the master or slave device normally it is output by the device that receives 8 bit data The serial clock SCL is continuously output by the master device However in the slave device the SCL s low level period can be extended and a wait can be inserted 1 Start condition A start condition is met when the SC...

Page 234: ...ects the start condition and checks whether or not the 7 bit address data matches the data values stored in the slave address register SVA0 If the address data matches the SVA0 values the slave device is selected and communicates with the master device until the master device transmits a start condition or stop condition Figure 10 15 Address Address SCL 1 SDA INTIIC0 Note 2 3 4 5 6 7 8 9 A6 A5 A4 ...

Page 235: ...hat the master device is transmitting data to a slave device When the transfer direction specification bit has a value of 1 it indicates that the master device is receiving data from a slave device Figure 10 16 Transfer Direction Specification SCL 1 SDA INTIIC0 2 3 4 5 6 7 8 9 A6 A5 A4 A3 A2 A1 A0 R W Transfer direction specification Note Note INTIIC0 is not issued if data other than a local addre...

Page 236: ... final data was received When the receiving device sets the SDA line to low level during the ninth clock the ACK signal becomes active normal receive response When bit 2 ACKE of the IIC control register IICC0 is set to 1 automatic ACK signal generation is enabled Transmission of the eighth bit following the 7 address data bits causes bit 3 TRC of the IIC status register IICS0 to be set When this T...

Page 237: ...ted ACK signal is automatically output at the falling edge of the SCL s eighth clock if ACKE has already been set to 1 5 Stop condition When the SCL pin is at high level changing the SDA pin from low level to high level generates a stop condition A stop condition is a signal that the master device outputs to the slave device when serial transfer has been completed The slave device includes hardwar...

Page 238: ...both the master and slave devices the next data transfer can begin Figure 10 19 Wait Signal 1 2 1 When master device has a nine clock wait and slave device has an eight clock wait master transmits slave receives and ACKE 1 SCL 6 SDA 7 8 9 1 2 3 SCL IIC0 6 H 7 8 1 2 3 D2 D1 D0 ACK D7 D6 D5 9 IIC0 SCL ACKE Master Master returns to high impedance but slave is in wait state low level Wait after output...

Page 239: ...rding to previously set ACKE value Transfer lines Remarks ACKE Bit 2 of IIC control register IICC0 WREL Bit 5 of IIC control register IICC0 A wait may be automatically generated depending on the setting for bit 3 WTIM of the IIC control register IICC0 Normally when bit 5 WREL of IICC0 is set to 1 or when FFH is written to the IIC shift register IIC0 the wait status is canceled and the transmitting...

Page 240: ...Address Data Data Stop normal transmission reception 1 When WTIM 0 ST AD6 AD0 RW AK D7 D0 AK D7 D0 AK SP 1 2 3 4 1 IICS0 10XXX110B 2 IICS0 10XXX000B 3 IICS0 10XXX000B 4 IICS0 00000001B Remarks Always generated Generated only when SPIE 1 X don t care 2 When WTIM 1 ST AD6 AD0 RW AK D7 D0 AK D7 D0 AK SP 1 2 3 4 1 IICS0 10XXX110B 2 IICS0 10XXX100B 3 IICS0 10XXXX00B 4 IICS0 00000001B Remarks Always gen...

Page 241: ... 10XXX110B 2 IICS0 10XXX000B 3 IICS0 10XXX110B 4 IICS0 10XXX000B 5 IICS0 00000001B Remarks Always generated Generated only when SPIE 1 X don t care 2 When WTIM 1 ST AD6 AD0 RW AK D7 D0 AK ST AD6 AD0 RW AK D7 D0 AK SP 1 2 3 4 5 1 IICS0 10XXX110B 2 IICS0 10XXX000B 3 IICS0 10XXX110B 4 IICS0 10XXXX00B 5 IICS0 00000001B Remarks Always generated Generated only when SPIE 1 X don t care ...

Page 242: ...K SP 1 2 3 4 1 IICS0 1010X110B 2 IICS0 1010X000B 3 IICS0 1010X000B 4 IICS0 00000001B Remarks Always generated Generated only when SPIE 1 X don t care 2 When WTIM 1 ST AD6 AD0 RW AK D7 D0 AK D7 D0 AK SP 1 2 3 4 1 IICS0 1010X110B 2 IICS0 1010X100B 3 IICS0 1010XX00B 4 IICS0 00000001B Remarks Always generated Generated only when SPIE 1 X don t care ...

Page 243: ...AD0 RW AK D7 D0 AK D7 D0 AK SP 1 2 3 4 1 IICS0 0001X110B 2 IICS0 0001X000B 3 IICS0 0001X000B 4 IICS0 00000001B Remarks Always generated Generated only when SPIE 1 X don t care 2 When WTIM 1 ST AD6 AD0 RW AK D7 D0 AK D7 D0 AK SP 1 2 3 4 1 IICS0 0001X110B 2 IICS0 0001X100B 3 IICS0 0001XX00B 4 IICS0 00000001B Remarks Always generated Generated only when SPIE 1 X don t care ...

Page 244: ...1X110B 2 IICS0 0001X000B 3 IICS0 0001X110B 4 IICS0 0001X000B 5 IICS0 00000001B Remarks Always generated Generated only when SPIE 1 X don t care 2 When WTIM 1 after restart matches with SVA0 ST AD6 AD0 RW AK D7 D0 AK ST AD6 AD0 RW AK D7 D0 AK SP 1 2 3 4 5 1 IICS0 0001X110B 2 IICS0 0001XX00B 3 IICS0 0001X110B 4 IICS0 0001XX00B 5 IICS0 00000001B Remarks Always generated Generated only when SPIE 1 X d...

Page 245: ...CS0 0001X000B 3 IICS0 0010X010B 4 IICS0 0010X000B 5 IICS0 00000001B Remarks Always generated Generated only when SPIE 1 X don t care 2 When WTIM 1 after restart extension code reception ST AD6 AD0 RW AK D7 D0 AK ST AD6 AD0 RW AK D7 D0 AK SP 1 2 3 4 5 6 1 IICS0 0001X110B 2 IICS0 0001XX00B 3 IICS0 0010X010B 4 IICS0 0010X110B 5 IICS0 0010XX00B 6 IICS0 00000001B Remarks Always generated Generated only...

Page 246: ... 2 3 4 1 IICS0 0001X110B 2 IICS0 0001X000B 3 IICS0 0000XX10B 4 IICS0 00000001B Remarks Always generated Generated only when SPIE 1 X don t care 2 When WTIM 1 after restart does not match with address not extension code ST AD6 AD0 RW AK D7 D0 AK ST AD6 AD0 RW AK D7 D0 AK SP 1 2 3 4 1 IICS0 0001X110B 2 IICS0 0001XX00B 3 IICS0 0000XX10B 4 IICS0 00000001B Remarks Always generated Generated only when S...

Page 247: ...0 AK SP 1 2 3 4 1 IICS0 0010X010B 2 IICS0 0010X000B 3 IICS0 0010X000B 4 IICS0 00000001B Remarks Always generated Generated only when SPIE 1 X don t care 2 When WTIM 1 ST AD6 AD0 RW AK D7 D0 AK D7 D0 AK SP 1 2 3 4 5 1 IICS0 0010X010B 2 IICS0 0010X110B 3 IICS0 0010X100B 4 IICS0 0010XX00B 5 IICS0 00000001B Remarks Always generated Generated only when SPIE 1 X don t care ...

Page 248: ...CS0 0010X000B 3 IICS0 0001X110B 4 IICS0 0001X000B 5 IICS0 00000001B Remarks Always generated Generated only when SPIE 1 X don t care 2 When WTIM 1 after restart matches with SVA0 ST AD6 AD0 RW AK D7 D0 AK ST AD6 AD0 RW AK D7 D0 AK SP 1 2 3 4 5 6 1 IICS0 0010X010B 2 IICS0 0010X110B 3 IICS0 0010XX00B 4 IICS0 0001X110B 5 IICS0 0001XX00B 6 IICS0 00000001B Remarks Always generated Generated only when S...

Page 249: ...B 3 IICS0 0010X010B 4 IICS0 0010X000B 5 IICS0 00000001B Remarks Always generated Generated only when SPIE 1 X don t care 2 When WTIM 1 after restart extension code reception ST AD6 AD0 RW AK D7 D0 AK ST AD6 AD0 RW AK D7 D0 AK SP 1 2 3 4 5 6 7 1 IICS0 0010X010B 2 IICS0 0010X110B 3 IICS0 0010XX00B 4 IICS0 0010X010B 5 IICS0 0010X110B 6 IICS0 0010XX00B 7 IICS0 00000001B Remarks Always generated Genera...

Page 250: ...CS0 0010X010B 2 IICS0 0010X000B 3 IICS0 00000X10B 4 IICS0 00000001B Remarks Always generated Generated only when SPIE 1 X don t care 2 When WTIM 1 after restart does not match with address not extension code ST AD6 AD0 RW AK D7 D0 AK ST AD6 AD0 RW AK D7 D0 AK SP 1 2 3 4 5 1 IICS0 0010X010B 2 IICS0 0010X110B 3 IICS0 0010XX00B 4 IICS0 00000X10B 5 IICS0 00000001B Remarks Always generated Generated on...

Page 251: ...1 5 Arbitration loss operation operation as slave after arbitration loss a When arbitration loss occurs during transmission of slave address data 1 When WTIM 0 ST AD6 AD0 RW AK D7 D0 AK D7 D0 AK SP 1 2 3 4 1 IICS0 0101X110B Example when ALD is read during interrupt servicing 2 IICS0 0001X000B 3 IICS0 0001X000B 4 IICS0 00000001B Remarks Always generated Generated only when SPIE 1 X don t care ...

Page 252: ...00B 4 IICS0 00000001B Remarks Always generated Generated only when SPIE 1 X don t care b When arbitration loss occurs during transmission of extension code 1 When WTIM 0 ST AD6 AD0 RW AK D7 D0 AK D7 D0 AK SP 1 2 3 4 1 IICS0 0110X010B Example when ALD is read during interrupt servicing 2 IICS0 0010X000B 3 IICS0 0010X000B 4 IICS0 00000001B Remarks Always generated Generated only when SPIE 1 X don t ...

Page 253: ...rbitration loss a When arbitration loss occurs during transmission of slave address data ST AD6 AD0 RW AK D7 D0 AK D7 D0 AK SP 1 2 1 IICS0 01000110B Example when ALD is read during interrupt servicing 2 IICS0 00000001B Remarks Always generated Generated only when SPIE 1 X don t care b When arbitration loss occurs during transmission of extension code ST AD6 AD0 RW AK D7 D0 AK D7 D0 AK SP 1 2 1 IIC...

Page 254: ...S0 01000000B Example when ALD is read during interrupt servicing 3 IICS0 00000001B Remarks Always generated Generated only when SPIE 1 X don t care 2 When WTIM 1 ST AD6 AD0 RW AK D7 D0 AK D7 D0 AK SP 1 2 3 1 IICS0 10001110B 2 IICS0 01000100B Example when ALD is read during interrupt servicing 3 IICS0 00000001B Remarks Always generated Generated only when SPIE 1 X don t care ...

Page 255: ...00110B Example when ALD is read during interrupt servicing 3 IICS0 00000001B Remarks Always generated Generated only when SPIE 1 X don t care Dn D6 D0 2 Extension code ST AD6 AD0 RW AK D7 Dn ST AD6 AD0 RW AK D7 D0 AK SP 1 2 3 1 IICS0 1000X110B 2 IICS0 0110X010B Example when ALD is read during interrupt servicing IICC s LREL is set to 1 by software 3 IICS0 00000001B Remarks Always generated Generat...

Page 256: ... only when SPIE 1 X don t care Dn D6 D0 f When arbitration loss occurs due to low level data when attempting to generate a restart condition 1 When WTIM 0 STT 1 ST AD6 AD0 RW AK D7 D0 AK D7 D0 AK D7 D0 AK SP 1 2 3 4 1 IICS0 1000X110B 2 IICS0 1000X000B 3 IICS0 01000000B Example when ALD is read during interrupt servicing 4 IICS0 00000001B Remarks Always generated Generated only when SPIE 1 X don t ...

Page 257: ...read during interrupt servicing 4 IICS0 00000001B Remarks Always generated Generated only when SPIE 1 X don t care g When arbitration loss occurs due to a stop condition when attempting to generate a restart condition 1 When WTIM 0 STT 1 ST AD6 AD0 RW AK D7 D0 AK SP 1 2 3 1 IICS0 1000X110B 2 IICS0 1000X000B 3 IICS0 01000001B Remarks Always generated Generated only when SPIE 1 X don t care ...

Page 258: ...ly when SPIE 1 X don t care h When arbitration loss occurs due to low level data when attempting to generate a stop condition 1 When WTIM 0 SPT 1 ST AD6 AD0 RW AK D7 D0 AK D7 D0 AK D7 D0 AK SP 1 2 3 4 1 IICS0 1000X110B 2 IICS0 1000X000B 3 IICS0 01000000B Example when ALD is read during interrupt servicing 4 IICS0 00000001B Remarks Always generated Generated only when SPIE 1 X don t care ...

Page 259: ...M 1 SPT 1 ST AD6 AD0 RW AK D7 D0 AK D7 D0 AK D7 D0 AK SP 1 2 3 4 1 IICS0 1000X110B 2 IICS0 1000XX00B 3 IICS0 01000000B Example when ALD is read during interrupt servicing 4 IICS0 00000001B Remarks Always generated Generated only when SPIE 1 X don t care ...

Page 260: ... 9 Note 2 9 Note 2 9 9 9 Notes 1 The slave device s INTIIC0 signal and wait period occurs at the falling edge of the ninth clock only when there is a match with the address set to the slave address register SVA0 At this point ACK is output regardless of the value set to IICC0 s bit 2 ACKE For a slave device that has received an extension code INTIIC0 occurs at the falling edge of the eighth clock ...

Page 261: ...llation methods are as follows By setting bit 5 WREL of IIC control register IICC0 to 1 By writing to the IIC shift register IIC0 When 8 clock wait has been selected WTIM 0 the output level of ACK must be determined prior to wait cancellation 5 Stop condition detection INTIIC0 is generated when a stop condition is detected 10 3 7 Address match detection method When in I 2 C bus mode the master dev...

Page 262: ...110XX is set to SVA0 by a 10 bit address transfer and 111110XX0 is transferred from the master device the results are as follows Note that INTIIC0 occurs at the falling edge of the eighth clock High order four bits of data match EXC 1 Note Seven bits of data match COI 1 Note Note EXC Bit 5 of IIC status register IICS0 COI Bit 4 of IIC status register IICS0 3 Since the processing after the interrup...

Page 263: ...itration an arbitration loss flag ALD in the IIC status register IICS0 is set via the timing by which the arbitration loss occurred and the SCL and SDA lines are both set for high impedance which releases the bus The arbitration loss is detected based on the timing of the next interrupt request the eighth or ninth clock when a stop condition is detected etc and the ALD 1 setting that has been made...

Page 264: ...mission During data transmission During ACK signal transfer period after data transmission When restart condition is detected during data transfer When stop condition is detected during data transfer When stop condition is output when SPIE 1 Note 2 When data is at low level while attempting to output a restart condition At falling edge of eighth or ninth clock following byte transfer Note 1 When s...

Page 265: ...ction that generates an interrupt request INTIIC0 when a local address and extension code have been received This function makes processing more efficient by preventing unnecessary interrupt requests from occurring when addresses do not match When a start condition is detected wake up standby mode is set This wake up standby mode is in effect while addresses are transmitted due to the possibility ...

Page 266: ...n the bus release is detected when a stop condition is detected writing to the IIC shift register IIC0 causes the master s address transfer to start At this point IICC0 s bit 4 SPIE should be set When STT has been set the operation mode as start condition or as communication reservation is determined according to the bus status If the bus has been released a start condition is generated If the bus...

Page 267: ...unication reservation Set STD Output by master with bus access IIC0 IIC shift register STT Bit 1 of IIC control register IICC0 STD Bit 1 of IIC status register IICS0 SPD Bit 0 of IIC status register IICS0 Communication reservations are accepted via the following timing After bit 1 STD of the IIC status register IICS0 is set to 1 a communication reservation can be made by setting bit 1 STT of the I...

Page 268: ...CHAPTER 10 SERIAL INTERFACE FUNCTION 268 Figure 10 22 Timing for Accepting Communication Reservations SCL SDA STD SPD Standby mode ...

Page 269: ... MSTS 0 Communication reservation Note Generate start condition Sets STT flag communication reservation Gets wait period set by software see Table 10 6 Confirmation of communication reservation Clear user flag IIC0 write operation Defines that communication reservation is in effect defines and sets user flag to any part of RAM Note The communication reservation operation executes a write to the II...

Page 270: ...t generate a stop condition to release the bus then perform master device communication When using multiple masters it is not possible to perform master device communication when the bus has not been released when a stop condition has not been detected Use the following sequence for generating a stop condition a Set IIC clock select register IICCL0 b Set bit 7 IICE of the IIC control register IICC...

Page 271: ...WTIM 1 Start IIC0 write transfer Start IIC0 write transfer WREL 1 Start reception Generate stop condition no slave with matching address Generate restart condition or stop condition START Data processing Data processing ACKE 0 No Yes No No No No No No Yes Yes Yes Yes Yes INTIIC0 1 WTIM 0 ACKE 1 INTIIC0 1 Transfer completed INTIIC0 1 ACKD 1 TRC 1 INTIIC0 1 ACKD 1 Stop condition detection Address tr...

Page 272: ...ow Chart IICC0 H IICE 1 WREL 1 Start reception Detect restart condition or stop condition START ACKE 0 Data processing Data processing LREL 1 No Yes No No No No No No No Yes No Yes Yes Yes Yes Yes Yes WTIM 0 ACKE 1 INTIIC0 1 Yes Communicate Transfer completed INTIIC0 1 WTIM 1 Start IIC0 write transfer INTIIC0 1 EXC 1 COI 1 TRC 1 ACKD 1 ...

Page 273: ...he TRC bit bit 3 of the IIC status register IICS0 that specifies the data transfer direction and then starts serial communication with the slave device Figures 10 26 and 10 27 show timing charts of the data communication The IIC bus shift register IIC0 s shift operation is synchronized with the falling edge of the serial clock SCL The transmit data is transferred to the SO latch and is output MSB ...

Page 274: ...IM H H L L L L H H H L L ACKE MSTS STT SPT WREL INTIIC0 TRC IIC0 ACKD STD SPD WTIM ACKE MSTS STT SPT WREL INTIIC0 TRC SCL SDA Processing by master device Transfer lines Processing by slave device 1 2 3 4 5 6 7 8 9 4 3 2 1 A6 A5 A4 A3 A2 A1 A0 W ACK D4 D5 D6 D7 IIC0 address IIC0 data IIC0 FFH Transmit Start condition Receive When EXC 1 Note Note Note To cancel slave wait write FFH to IIC0 or set WR...

Page 275: ...L L L L L H H H H L L L L L ACKE MSTS STT SPT WREL INTIIC0 TRC IIC0 ACKD STD SPD WTIM ACKE MSTS STT SPT WREL INTIIC0 TRC SCL SDA Processing by master device Transfer lines Processing by slave device 1 9 8 2 3 4 5 6 7 8 9 3 2 1 D7 D0 D6 D5 D4 D3 D2 D1 D0 D5 D6 D7 IIC0 data IIC0 FFH Note IIC0 FFH Note IIC0 data Transmit Receive Note Note Note To cancel slave wait write FFH to IIC0 or set WREL ...

Page 276: ... L ACKE MSTS STT SPT WREL INTIIC0 TRC IIC0 ACKD STD SPD WTIM ACKE MSTS STT SPT WREL INTIIC0 TRC SCL SDA Processing by master device Transfer lines Processing by slave device 1 2 3 4 5 6 7 8 9 2 1 D7 D6 D5 D4 D3 D2 D1 D0 A5 A6 IIC0 data IIC0 address IIC0 FFH Note IIC0 FFH Note Stop condition Start condition Transmit Note Note When SPIE 1 Receive When SPIE 1 Note To cancel slave wait write FFH to II...

Page 277: ...KD STD SPD WTIM H H L L H H L ACKE MSTS STT L L SPT WREL INTIIC0 TRC IIC0 ACKD STD SPD WTIM ACKE MSTS STT SPT WREL INTIIC0 TRC SCL SDA Processing by master device Transfer lines Processing by slave device 1 2 3 4 5 6 7 8 9 4 5 6 3 2 1 A6 A5 A4 A3 A2 A1 A0 R D4 D3 D2 D5 D6 D7 IIC0 address IIC0 FFH Note Note IIC0 data Start condition Note To cancel slave wait write FFH to IIC0 or set WREL ...

Page 278: ...L L L L H H H L L L L L ACKE MSTS STT SPT WREL INTIIC0 TRC IIC0 ACKD STD SPD WTIM ACKE MSTS STT SPT WREL INTIIC0 TRC SCL SDA Processing by master device Transfer lines Processing by slave device 1 8 9 2 3 4 5 6 7 8 9 3 2 1 D7 D0 ACK D6 D5 D4 D3 D2 D1 D0 ACK D5 D6 D7 Note Note Receive Transmit IIC0 data IIC0 data IIC0 FFH Note IIC0 FFH Note Note To cancel slave wait write FFH to IIC0 or set WREL ...

Page 279: ... H H L L L H H ACKE MSTS STT SPT WREL INTIIC0 TRC IIC0 ACKD STD SPD WTIM ACKE MSTS STT SPT WREL INTIIC0 TRC SCL SDA Processing by master device Transfer lines Processing by slave device 1 2 3 4 5 6 7 8 9 2 1 D7 D6 D5 D4 D3 D2 D1 D0 A5 A6 IIC0 address IIC0 FFH Note Note IIC0 data Stop condition Start condition When SPIE 1 N ACK When SPIE 1 Note To cancel slave wait write FFH to IIC0 or set WREL ...

Page 280: ...s using a wide range of selectable baud rates In addition a baud rate based on divided clock input to the ASCKn pin can also be defined The UARTn baud rate generator can also be used to generate a MIDI standard baud rate 31 25 kbps 10 4 1 Configuration The UART includes the following hardware Table 10 7 Configuration of UARTn Item Configuration Registers Transmit shift register 0 1 TXS0 TXS1 Recei...

Page 281: ...XSn is transmitted as serial data When the data length is set as 7 bits bit 0 to bit 6 of the data written to TXSn is transmitted as serial data Writing data to TXSn starts the transmit operation TXSn can be written to by an 8 bit memory manipulation instruction It cannot be read from RESET input sets these registers to FFH Caution Do not write to TXSn during a transmit operation 2 Receive shift r...

Page 282: ...ircuit The reception control circuit controls receive operations based on the values set to the asynchronous serial interface mode register ASIMn During a receive operation it performs error checking such as for parity errors and sets various values to the asynchronous serial interface status register ASISn according to the type of error that is detected 10 4 2 UARTn control registers The UARTn us...

Page 283: ...RTn mode transmit and receive Serial function Serial function PS1n PS0n Parity Bit Specification 0 0 No parity 0 1 Zero parity always added during transmission No parity detection during reception parity errors do not occur 1 0 Odd parity 1 1 Even parity UCLn Character Length Specification 0 7 bits 1 8 bits SLn Stop Bit Length Specification for Transmit Data 0 1 bit 1 2 bits ISRMn Receive Completi...

Page 284: ...No parity error 1 Parity error Transmit data parity does not match FEn Framing Error Flag 0 No framing error 1 Framing error Note 1 Stop bit not detected OVEn Overrun Error Flag 0 No overrun error 1 Overrun error Note 2 Next receive operation was completed before data was read from receive buffer register Notes 1 Even if a stop bit length of two bits has been set to bit 2 SLn in the asynchronous s...

Page 285: ... 0 0 0 0 1 0 1 1 fSCK 11 11 0 0 0 0 1 1 0 0 fSCK 12 12 0 0 0 0 1 1 0 1 fSCK 13 13 0 0 0 0 1 1 1 0 fSCK 14 14 0 0 0 0 1 1 1 1 fSCK 15 15 0 0 0 1 0 0 0 0 fSCK 16 16 1 1 1 1 1 1 1 1 fSCK 255 255 Cautions 1 Before starting operation select a setting other than Setting prohibited Selecting the Setting prohibited setting in stop mode does not cause any problems 2 If write is performed to BRGCn during co...

Page 286: ... 0 0 0 External clock ASCKn 0 0 1 fxx 17 MHz 0 0 1 0 fxx 2 8 5 MHz 1 0 1 1 fxx 4 4 25 MHz 2 1 0 0 fxx 8 2 13 MHz 3 1 0 1 fxx 16 1 06 MHz 4 1 1 0 fxx 32 531 kHz 5 1 1 1 at n 0 TM3 output at n 1 TM2 output Caution If write is performed to BRGMCn during communication processing the output of the baud rate generator will be disturbed and communication will not be performed normally Therefore do not wr...

Page 287: ... mode register ASIMn ASIMn can be set by a 1 bit or 8 bit memory manipulation instruction RESET input sets the ASIMn to 00H After reset 00H R W Address FFFFF300H FFFFF310H 7 6 5 4 3 2 1 0 ASIMn TXEn RXEn PS1n PS0n CLn SLn ISRMn 0 n 0 1 TXEn RXEn Operation Mode RXDn Pxx Pin Function TXDn Pxx Pin Function 0 0 Operation stop Port function Port function 0 1 UARTn mode receive only Serial function Port...

Page 288: ...enerator enables communications using a wide range of selectable baud rates The UARTn baud rate generator can also be used to generate a MIDI standard baud rate 31 25 kbps 1 Register settings UARTn mode settings are made via the asynchronous serial interface mode register ASIMn asynchronous serial interface status register ASISn baud rate generator control register BRGCn and the baud rate generato...

Page 289: ...mit only Port function Serial function 1 1 UARTn mode transmit and receive Serial function Serial function PS1n PS0n Parity Bit Specification 0 0 No parity 0 1 Zero parity always added during transmission No parity detection during reception parity errors do not occur 1 0 Odd parity 1 1 Even parity CLn Character Length Specification 0 7 bits 1 8 bits SLn Stop Bit Length Specification for Transmit ...

Page 290: ...ag 0 No framing error 1 Framing error Note 1 Stop bit not detected OVEn Overrun Error Flag 0 No overrun error 1 Overrun error Note 2 Next receive operation was completed before data was read from receive buffer register Notes 1 Even if a stop bit length of two bits has been set to bit 2 SLn in the asynchronous serial interface mode register ASIMn stop bit detection during a receive operation only ...

Page 291: ... 1 0 0 1 fSCK 9 9 0 0 0 0 1 0 1 0 fSCK 10 10 0 0 0 0 1 0 1 1 fSCK 11 11 0 0 0 0 1 1 0 0 fSCK 12 12 0 0 0 0 1 1 0 1 fSCK 13 13 0 0 0 0 1 1 1 0 fSCK 14 14 0 0 0 0 1 1 1 1 fSCK 15 15 0 0 0 1 0 0 0 0 fSCK 16 16 1 1 1 1 1 1 1 1 fSCK 255 255 Cautions 1 Before starting operation select a setting other than Setting prohibited Selecting Setting prohibited setting in stop mode does not cause any problems 2 ...

Page 292: ...ck Selection m 0 0 0 External clock ASCKn 0 0 1 fxx 17 MHz 0 0 1 0 fxx 2 8 5 MHz 1 0 1 1 fxx 4 4 25 MHz 2 1 0 0 fxx 8 2 13 MHz 3 1 0 1 fxx 16 1 06 MHz 4 1 1 0 fxx 32 531 kHz 5 1 1 1 at n 0 TM3 output at n 1 TM2 output Caution If write is performed to BRGMCn during communication processing the output of the baud rate generator is disturbed and communication will not be performed normally Therefore ...

Page 293: ... bits in a frame and the counter division ratio 1 16 k Table 10 8 shows the relation between the main clock and the baud rate and Figure 10 33 shows an example of the baud rate tolerance Table 10 8 Relation between Main Clock and Baud Rate Baud Rate fxx 17 MHz fxx 10 MHz fxx 5 MHz bps k m Error k m Error k m Error 1200 221 5 0 16 130 5 0 16 130 4 0 16 2400 221 4 0 16 130 4 0 16 130 3 0 16 4800 221...

Page 294: ...lock cycle T enabling normal reception START D0 D7 P STOP Low speed clock clock cycle T enabling normal reception START D0 D7 P STOP 32T 64T 256T 288T 320T 352T Ideal sampling point 304T 336T 30 45T 60 9T 304 5T 15 5T 15 5T 0 5T Sampling error 33 55T 67 1T 301 95T 335 5T Remark T 5 bit counter s source clock cycle Baud rate error tolerance when k 0 100 4 8438 15 5 320 ...

Page 295: ...ty bit Stop bit 1 data frame Start bit 1 bit Character bits 7 bits or 8 bits Parity bit Event parity odd parity zero parity or no parity Stop bit s 1 bit or 2 bits When 7 bits is selected as the number of character bits only the low order 7 bits from bit 0 to bit 6 are valid so that during a transmission the highest bit bit 7 is ignored and during reception the highest bit bit 7 must be set to 0 T...

Page 296: ... value is 0 During reception The number of 1 bits is counted among the receive data including a parity bit and a parity error is generated when the result is an odd number b Odd parity During transmission The number of bits in transmit data including a parity bit is controlled so that the number is set an odd number of 1 bits The value of the parity bit is as follows If the transmit data contains ...

Page 297: ... issued The timing of the transmit completion interrupt is shown in Figure 10 35 Figure 10 35 Timing of Asynchronous Serial Interface Transmit Completion Interrupt TxDn output D0 D1 D2 D6 D7 Parity STOP START INTSTn a Stop bit length 1 TxDn output D0 D1 D2 D6 D7 Parity START INTSTn b Stop bit length 2 STOP Caution Do not write to the asynchronous serial interface mode register ASIMn during a trans...

Page 298: ...data in the shift register is transferred to the receive buffer register RXBn and a receive completion interrupt INTSRn occurs Even if an error has occurred the receive data in which the error occurred is still transferred to RXBn When an error occurs INSTRn is generated if bit 1 ISRMn of ASIMn is cleared 0 On the other hand INSTRn is not generated if the ISRMn bit is set 1 If the RXEn bit is rese...

Page 299: ... is set Table 10 9 Receive Error Causes Receive error Cause ASISn value Parity error Parity specification at transmission and receive data parity do not match 04H Framing error Stop bit is not detected 02H Overrun error Reception of subsequent data was completed before data was read from the receive buffer register 01H Figure 10 37 Receive Error Timing RxDn Input INTSRn Note D7 D6 D2 D1 D0 Parity ...

Page 300: ... register n TXSn and receive buffer register n RXBn are stopped and their values immediately before the clock stopped are hold The TXDn output pin holds the data immediately before the clock is stopped in STOP mode during transmission When the clock is stopped during reception the receive data until the clock stopped are stored and subsequent receive operation is stopped Reception resumes upon clo...

Page 301: ...ising edge falling edge or both rising and falling edges can be specified 2 Software start Conversion is started by setting A D converter mode register ADM One analog input channel is selected from ANI0 through ANI11 and A D conversion is performed If A D conversion has been started by means of hardware start conversion stops after it has been completed and an interrupt request INTAD is generated ...

Page 302: ...VDD AVREF AVSS INTAD 4 ADS3 ADS2 ADS1 ADS0 ADCS TRG FR2 FR1 FR0 EGA1 EGA0 ADPS Selector Sample hold circuit AVSS Voltage comparator Tap selector Successive approximation register SAR ADTRG Edge detection circuit Control circuit A D conversion result register ADCR0n Trigger enable Analog input channel specification register ADS A D converter mode register ADM Internal bus ...

Page 303: ...ister SAR The upper 10 bits of this register holds the result of the A D conversion the lower 6 bits are fixed to 0 This register is read using a 16 bit memory manipulation instruction RESET input sets ADCR to 0000H When using only upper 8 bits of the result of the A D conversion ADCRH is read using an 8 bit memory manipulation instruction RESET input sets ADCRH to 00H Caution When the write opera...

Page 304: ...te maximum ratings is input to a channel the conversion value of the channel is undefined and the conversion values of the other channels may also be affected 7 AVREF pin This pin inputs a reference voltage to the A D converter The signals input to the ANI0 through ANI11 pins are converted into digital signals based on the voltage applied across AVREF and AVSS 8 AVSS pin This is the ground pin of ...

Page 305: ...ignal to be converted into a digital signal starting or stopping the conversion and an external trigger ADM is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets ADM to 00H Figure 11 2 Format of A D Converter Mode Register ADM 1 2 After reset 00H R W Address FFFFF3C0H 7 6 5 4 3 2 1 0 ADM ADCS TRG FR2 FR1 FR0 EGA1 EGA0 ADPS ADCS A D Conversion Control 0 Stops conversion 1 Enab...

Page 306: ...8 fxx 144 fxx 25 4 µs 54 0 µs 1 0 0 1 216 fxx 108 fxx 19 1 µs 40 5 µs 1 0 1 0 168 fxx 84 fxx 14 9 µs 31 5 µs 1 0 1 1 120 fxx 60 fxx 10 7 µs 22 5 µs 1 1 0 0 96 fxx 58 fxx 8 4 µs 18 0 µs 1 1 0 1 72 fxx 36 fxx Setting prohibited 13 5 µs 1 1 1 0 60 fxx 30 fxx Setting prohibited 11 3 µs 1 1 1 1 48 fxx 24 fxx Setting prohibited 9 0 µs EGA1 EGA0 Specification of Edge Detection of External Trigger Signal ...

Page 307: ...uction RESET input sets ADS to 00H Figure 11 3 Format of Analog Input Channel Specification Register ADS After reset 00H R W Address FFFFF3C2H 7 6 5 4 3 2 1 0 ADS 0 0 0 0 ADS3 ADS2 ADS1 ADS0 ADS3 ADS2 ADS1 ADS0 Analog Input Channel Specification 0 0 0 0 ANI0 0 0 0 1 ANI1 0 0 1 0 ANI2 0 0 1 1 ANI3 0 1 0 0 ANI4 0 1 0 1 ANI5 0 1 1 0 ANI6 0 1 1 1 ANI7 1 0 0 0 ANI8 1 0 0 1 ANI9 1 0 1 0 ANI10 1 0 1 1 AN...

Page 308: ... voltage is less than 1 2 AVREF the MSB is reset 6 Next bit 8 of the SAR is automatically set and the analog input voltage is compared again Depending on the value of bit 9 to which the result of the preceding comparison has been set the voltage tap of the series resistor string is selected as follows Bit 9 1 3 4 AVREF Bit 9 0 1 4 AVREF The analog input voltage is compared with one of these voltag...

Page 309: ...rsion result A D conversion is successively executed until the bit 7 ADCS of the A D converter mode register ADM is reset to 0 by software If the ADM and analog input channel specification register ADS are written during A D conversion the conversion is initialized If ADCS is set to 1 at this time conversion is started from the beginning RESET input sets the A D conversion result register ADCR to ...

Page 310: ...Function that returns integer of value in VIN Analog input voltage AVREF AVREF pin voltage ADCR Value of the A D conversion result register ADCR Figure 11 5 shows the relation between the analog input voltage and A D conversion result Figure 11 5 Relation between Analog Input Voltage and A D Conversion Result 1 1 3 2 5 3 2043 1022 20451023 2047 1 2048 102420481024 2048 1024 2048 1024 20481024 2048...

Page 311: ...on is executed The A D conversion can be started in the following two ways Hardware start Started by trigger input ADTRG rising edge falling edge or both rising and falling edges can be specified Software start Started by setting A D converter mode register ADM The result of the A D conversion is stored to the A D conversion result register ADCR and an interrupt request signal INTAD is generated a...

Page 312: ...started and completed conversion is not started again unless a new external trigger signal is input If data with ADCS set to 1 is written to ADM during conversion the conversion under execution is stopped and the A D converter stands by until a new external trigger signal is input If the external trigger signal is input A D conversion is executed again from the beginning If data with ADCS set to 0...

Page 313: ...enerated Once A D conversion has been started and completed the next conversion is started immediately A D conversion is repeated until new data is written to ADS If ADS is rewritten during conversion the conversion under execution is stopped and conversion of the newly selected analog input channel is started If data with ADCS set to 0 is written to ADM during A D conversion the conversion is imm...

Page 314: ...maximum ratings is input to a channel the converted value of the channel becomes undefined Moreover the values of the other channels may also be affected 3 Conflict 1 Conflict between writing A D conversion result register ADCR and reading ADCR at end of conversion Reading ADCR takes precedence After ADCR has been read a new conversion result is written to ADCR 2 Conflict between writing ADCR and ...

Page 315: ... through ANI11 pins are multiplexed with port pins To execute A D conversion with any of ANI0 through ANI11 selected do not execute an instruction that inputs data to the port during conversion otherwise the resolution may drop If a digital pulse is applied to pins adjacent to the pin whose input signal is converted into a digital signal the expected A D conversion result may not be obtained becau...

Page 316: ...ANIm conversion starts ADIF is set but conversion of ANIm is not completed A D conversion ADCR INTAD ANIn ANIn ANIm ANIm ANIm ANIn ANIn ANIm Remarks 1 n 0 1 11 2 m 0 1 11 8 AVDD pin The AVDD pin is the power supply pin of the analog circuit and also supplies power to the input circuit of ANI0 through ANI11 Even in an application where a back up power supply is used therefore be sure to apply the s...

Page 317: ... Request When a DMA transfer is completed and the TCn bit in the corresponding DMA channel control register DCHCn has been set to 1 a DMA transfer completion interrupt request INTDMA0 to INTDMA2 occurs on each channel in relation to the interrupt controller 12 3 Control Registers 1 DMA peripheral I O address registers 0 to 2 DIOA0 to DIOA2 These registers are used to set the peripheral I O registe...

Page 318: ... 2 DBC0 to DBC2 These are 8 bit registers that are used to set the number of transfers for DMA channel n The remaining number of transfers is retained during the DMA transfers A value of 1 is decremented once per transfer if the transfer is a byte 8 bit transfer or a value of 2 is decremented once per transfer if the transfer is a 16 bit transfer The transfers are ended when a borrow operation occ...

Page 319: ... TTYPn1 TTYPn0 TDIRn DSn ENn n 0 2 TCn DMA Transfer Completed Not Completed Note 0 Not completed 1 Completed Note This bit is set to 1 when a DMA transfer is ended by a terminal count It is cleared to 0 by a write instruction DADn On chip RAM Address Count Direction Control 0 Increment 1 Address is fixed Channel n TTYPn1 TTYPn0 Setting of Activation Source For DMA Transfer 0 0 0 INTCSI0 INTIIC0 No...

Page 320: ...m peripheral I Os to on chip RAM DSn Control of Transfer Data Size for DMA TransferNote 0 8 bit transfer 1 16 bit transfer ENn Control of DMA Transfer Enable Disable Status 0 Disable 1 Enable reset to 0 after DMA transfer is completed Note Make sure that the transfer format conforms to the peripheral I O register specifications access enabled data size read write etc for the DMA peripheral I O add...

Page 321: ... a real time output port Because RTO can output signals without jitter it is suitable for controlling a stepping motor The real time output port can be set in port mode or real time output port mode in 1 bit units Figure 13 1 shows the block diagram of RTO Figure 13 1 Block Diagram of RTO Output latch RTP0 RTP7 Real time output port mode register RTPM Real time output buffer register high order 4 ...

Page 322: ... in Figure 13 2 If an operation mode of 4 bits 2 channels is specified data can be independently set to RTBL and RTBH The data of both the registers can be read all at once by specifying the address of either of the registers If an operation mode of 8 bits 1 channel is specified 8 bit data can be set to both RTBL and RTBH by writing the data to either of the registers The data of both the register...

Page 323: ... RTBL RTBH RTBL RTBH RTBL RTBH RTBH RTBL RTBH RTBL Notes 1 Only the bits set in the real time output port mode RTPM can be read If a bit set in the port mode is read 0 is read 2 Set output data to RTBL and RTBH after setting the real time output port until the real time output trigger is generated 13 3 RTO Control Registers RTO is controlled by using the following two registers Real time output po...

Page 324: ...e Register RTPM After reset 00H R W Address FFFFF3A4H 7 6 5 4 3 2 1 0 RTPM RTPM7 RTPM6 RTPM5 RTPM4 RTPM3 RTPM2 RTPM1 RTPM0 RTPMn Selects Real Time Output Port n 0 to 7 0 Port mode 1 Real time output port mode Cautions 1 Set a port pin used as a real time output port pin in the output mode 2 Data cannot be set to the output latch of a port pin set as a real time output port pin To set an initial va...

Page 325: ...TPC RTPOE RTPEG BYTE EXTR 0 0 0 0 RTPOE Controls Operation of Real Time Output Port 0 Disables operation Note 1 Enables operation RTPEG Valid Edge of RTPTRG 0 Falling edge 1 Rising edge BYTE Operation Mode of Real Time Output Port 0 4 bits 2 channels 1 8 bits 1 channel EXTR Controls Real Time Output by RTPTRG Signal 0 Does not use RTPTRG as real time output trigger 1 Uses RTPTRG as real time outpu...

Page 326: ...s output from the bits of RTP0 to RTP7 The bits specified in the port mode by RTPM output 0 If the real time output operation is disabled by clearing RTPOE to 0 RTP0 to RTP7 output 0 regardless of the setting of RTPM Note EXTR Bit 4 of real time output port control register RTPC BYTE Bit 5 of real time output port control register RTPC Figure 13 5 Example of Operation Timing of RTO when EXTR 0 BYT...

Page 327: ... output buffer registers RTBH and RTBL 3 Enable the real time output operation Set RTPOE to 1 4 Set the next output to RTBH and RTBL until the selected transfer trigger is generated 5 Set the next real time output value to RTBH and RTBL by interrupt processing corresponding to the selected trigger 13 6 Notes 1 Before performing initialization disable the real time output operation by clearing bit ...

Page 328: ...328 MEMO ...

Page 329: ...uring output mode 0 Output 0 1 Output 1 Remark During input mode When the P0 register is read the pin levels at that time are read Writing to P0 writes the current pin levels to that register This does not affect the input pins During output mode When the P0 register is read the P0 register s values are read Writing to P0 writes values to that register and those values are immediately output Port ...

Page 330: ...st becomes invalid after a reset NMI and INTP0 to INTP6 do not function 2 Noise elimination a Elimination of noise from NMI and INTP0 to INTP3 pins An on chip noise elimination circuit uses analog delay to eliminate noise Consequently if a signal having a constant level is input for longer than a specified time to these pins it is detected as a valid edge Such edge detection occurs after the speci...

Page 331: ...M0 PM07 PM06 PM05 PM04 PM03 PM02 PM01 PM00 PM0n Control of I O Mode 0 Output mode 1 Input mode b Pull up resistance option register 0 PU0 Read and write in 8 bit units and bitwise are enabled Figure 14 3 Format of Pull up Resistance Option Register 0 PU0 After reset 00H R W Address FFFFF080H 7 6 5 4 3 2 1 0 PU0 PU07 PU06 PU05 PU04 PU03 PU02 PU01 PU00 PU0n Control of On Chip Pull Up Resistance Conn...

Page 332: ...rrupt request signal occurs at rising edge Remark n 0 Control of NMI pin n 1 to 7 Control of INTP0 to INTP6 pins d Falling edge enable register EGN0 Read and write in 8 bit units and bitwise are enabled Figure 14 5 Format of Falling Edge Enable Register EGN0 After reset 00H R W Address FFFFF0C2H 7 6 5 4 3 2 1 0 EGN0 EGN07 EGN06 EGN05 EGN04 EGN03 EGN02 EGN01 EGN00 EGN0n Control of Falling Edge Dete...

Page 333: ...he P1 register is read the pin levels at that time are read Writing to P1 writes the current pin levels to that register This does not affect the input pins During output mode When the P1 register is read the P1 register s values are read Writing to P1 writes values to that register and those values are immediately output Port 1 includes the following alternate function pins The SDA and SCL pins a...

Page 334: ...latch values can be read by reading the P1 register while in output mode A pull up resistance can be connected bitwise when specified via the pull up resistance option register 1 PU1 Clear to 0 the P1 register and the PM1 register when using alternate function pins as outputs The ORed result of the port output and the alternate function pin is output from the pins When a reset is input the setting...

Page 335: ...PU13 PU12 PU11 PU10 PU1n Control of On Chip Pull Up Resistance Connection 0 Do not connect 1 Connect c Port 1 function register PF1 Read and write in 8 bit units and bitwise are enabled Figure 14 9 Format of Port 1 Function Register PF1 After reset 00H R W Address FFFFF0A2H 7 6 5 4 3 2 1 0 PF1 0 0 PF15 PF14 0 Note PF12 PF11 PF10 PF1n Control of Normal Output N ch Open Drain Output 0 Normal output ...

Page 336: ... Control of Output Data during output mode 0 Output 0 1 Output 1 Remark During input mode When the P2 register is read the pin levels at that time are read Writing to P2 writes the current pin levels to that register This does not affect the input pins During output mode When the P2 register is read the P2 register s values are read Writing to P2 writes values to that register and those values are...

Page 337: ... be connected bitwise when specified via the pull up resistance option register 2 PU2 When using the alternate function as TI2 and TI3 pins noise elimination is provided by a digital noise elimination circuit same as digital noise elimination circuit for port 0 Clear to 0 the P2 register and the PM2 register when using alternate function pins as outputs The ORed result of the port output and the a...

Page 338: ... 1 0 PU2 PU27 PU26 PU25 PU24 PU23 PU22 PU21 PU20 PU2n Control of On Chip Pull Up Resistance Connection 0 Do not connect 1 Connect c Port 2 function register PF2 Read and write in 8 bit units and bitwise are enabled Figure 14 13 Format of Port 2 Function Register PF2 After reset 00H R W Address FFFFF0A4H 7 6 5 4 3 2 1 0 PF2 0 0 0 0 0 PF22 PF21 0 PF2n Control of Normal Output N ch Open Drain Output ...

Page 339: ...ut mode When the P3 register is read the pin levels at that time are read Writing to P3 writes the current pin levels to that register This does not affect the input pins During output mode When the P3 register is read the P3 register s values are read Writing to P3 writes values to that register and those values are immediately output Port 3 includes the following alternate function pins Pin Name...

Page 340: ...elimination is provided by a digital noise elimination circuit same as digital noise elimination circuit for port 0 When using the alternate function as A13 to A15 pins set the pin functions via the memory address output mode register MAM The PM3 register PM34 to PM36 must be set to 0 Clear to 0 the P3 register and the PM3 register when using alternate function pins as outputs The ORed result of t...

Page 341: ...bitwise Figure 14 17 Format of Ports 4 and 5 P4 and P5 After reset 00H R W Address FFFFF008H FFFFF00AH 7 6 5 4 3 2 1 0 Pn Pn7 Pn6 Pn5 Pn4 Pn3 Pn2 Pn1 Pn0 n 4 5 Pnx Control of Output Data during output mode 0 Output 0 1 Output 1 Remark During input mode When the P4 and P5 registers are read the pin levels at that time are read Writing to P4 and P5 writes the current pin levels to those registers Th...

Page 342: ...lues set to each bit are output to the port registers P4 and P5 When using these ports in input mode the pin statuses can be read by reading the P4 and P5 registers Also the P4 and P5 register output latch values can be read by reading the P4 and P5 registers while in output mode A software pull up function is not implemented When using the alternate function as AD0 to AD15 set the pin functions v...

Page 343: ... for which I O settings can be controlled bitwise Figure 14 19 Format of Port 6 P6 After reset 00H R W Address FFFFF00CH 7 6 5 4 3 2 1 0 P6 0 0 P65 P64 P63 P62 P61 P60 P6n Control of Output Data during output mode 0 Output 0 1 Output 1 Remark During input mode When the P6 register is read the pin levels at that time are read Writing to P6 writes the current pin levels to that register This does no...

Page 344: ...y reading the P6 register Also the P6 register output latch values can be read by reading the P6 register while in output mode A software pull up function is not implemented When using the alternate function as A16 to A21 set the pin functions via the memory expansion register MM This does not affect the PM6 register When a reset is input the settings are initialized to input mode 2 Control regist...

Page 345: ...0 P7 P77 P76 P75 P74 P73 P72 P71 P70 P7n Pin Level 0 1 Read pin level of bit n After reset undefined R Address FFFFF010H 7 6 5 4 3 2 1 0 P8 0 0 0 0 P83 P82 P81 P80 P8n Pin Level 0 1 Read pin level of bit n Ports 7 and 8 include the following alternate function pins Pin Name Alternate Function I O PULL Note Remark Port 7 P70 ANI0 Input No P71 ANI1 P72 ANI2 P73 ANI3 P74 ANI4 P75 ANI5 P76 ANI6 P77 AN...

Page 346: ...rt 9 P9 After reset 00H R W Address FFFFF012H 7 6 5 4 3 2 1 0 P9 0 P96 P95 P94 P93 P92 P91 P90 P9n Control of Output Data during output mode 0 Output 0 1 Output 1 Remark During input mode When the P9 register is read the pin levels at that time are read Writing to P9 writes the current pin levels to that register This does not affect the input pins During output mode When the P9 register is read t...

Page 347: ...tware pull up function is not implemented When using the P9 for control signals during expansion mode set the pin functions via the memory expansion register MM Since BVDD is used as the power supply if BVDD and VDD have different voltage values different I O levels will occur at ports 0 1 3 7 8 10 and 11 When a reset is input the settings are initialized to input mode 2 Control registers a Port 9...

Page 348: ... 1 Output 1 Remark During input mode When the P10 register is read the pin levels at that time are read Writing to P10 writes the current pin levels to that register This does not affect the input pins During output mode When the P10 register is read the P10 register s values are read Writing to P10 writes values to that register and those values are immediately output Port 10 includes the followi...

Page 349: ... can be connected bitwise when specified via the pull up resistance option register 10 PU10 When using the alternate function as A5 to A12 pins see the pin functions via the memory address output mode register MAM The PM10 register must be set to 0 Clear to 0 the P10 register and the PM10 register when using alternate function pins as outputs The ORed result of the port output and the alternate fu...

Page 350: ...t units and bitwise are enabled Figure 14 27 Format of Port 10 Function Register PF10 After reset 00H R W Address FFFFF0B4H 7 6 5 4 3 2 1 0 PF10 PF107 PF106 PF105 PF104 PF103 PF102 PF101 PF100 PF10n Control of Normal Output N ch Open Drain Output 0 Normal output 1 N ch open drain output 14 2 10 Port 11 Port 11 includes P114 which is an input only port as well as P110 to P113 which comprise an I O ...

Page 351: ... and those values are immediately output except for P114 Port 11 includes the following alternate function pins Pin Name Alternate Function I O PULLNote Remark Port 11 P110 A1 I O Yes P111 A2 P112 A3 P113 A4 P114 XT1 Input No Shared as sub clock XT1 pin Note Software pull up function 1 Function of P11 pins Port 11 is a 5 bit total port that includes P114 which is an input only port as well as P110...

Page 352: ... the sub clock is not being used Consequently leave the XT2 pin unconnected when the sub clock is not being used 2 Control registers a Port 11 mode register PM11 Read and write in 8 bit units and bitwise are enabled Figure 14 29 Format of Port 11 Mode Register PM11 After reset 1FH R W Address FFFFF036H 7 6 5 4 3 2 1 0 PM11 0 0 0 0 PM113 PM112 PM111 PM110 PM11n Control of I O Mode 0 Output mode 1 I...

Page 353: ...the P12 register is read the pin level at that time is read Writing to P12 writes the current pin level to that register This does not affect the input pins During output mode When the P12 register is read the P12 register s values are read Writing to P12 writes values to that register and those values are immediately output Port 12 includes the following alternate function pin Pin Name Alternate ...

Page 354: ... by reading the P12 register while in output mode Use the port mode control register PMC12 to specify use of P12 as the WAIT pin When a reset is input the settings are initialized to input mode Since BVDD is used as the power supply if BVDD and VDD have different voltage values different I O levels will occur at ports 0 1 3 7 8 10 and 11 2 Control registers a Port 12 mode register PM12 Read and wr...

Page 355: ...Read and write in 8 bit units and bitwise are enabled Figure 14 33 Format of Port 12 Mode Control Register PMC12 After reset 00H R W Address FFFFF058H 7 6 5 4 3 2 1 0 PMC12 0 0 0 0 0 0 0 PMC120 PMC120 Switching of Alternate Function 0 Use as port mode 1 Use as WAIT pin ...

Page 356: ...356 MEMO ...

Page 357: ...ration of the RESET pin 15 2 Pin Operations During the system reset period high impedance is set at almost all pins all pins except for RESET X2 XT2 VDD VSS AVDD AVSS BVDD BVSS and VPP Accordingly if connected to an external memory device be sure to attach pull up or pull down resistance for each pin in ports 3 to 6 and ports 9 to 11 If such resistance is not attached high impedance will be set fo...

Page 358: ...358 MEMO ...

Page 359: ...r by differentiating software Data adjustment in starting mass production is made easier 16 1 Features 4 byte 1 clock access in instruction fetch access All area one shot erase Communication through serial interface from the dedicated flash writer Erase write voltage VPP 7 8 V On board programming Number of rewrite 100 times target 16 2 Writing by Flash Writer Writing can be performed either on bo...

Page 360: ...uired for controlling the dedicated flash writer UART0 or CSI0 is used for the interface between the dedicated flash writer and the V850 SA1 to perform writing erasing etc A dedicated program adaptor FA Series required for off board writing 16 4 Communication System The communication between the dedicated flash writer and the V850 SA1 is performed by serial communication using UART0 or CSI0 1 UART...

Page 361: ...hpro II manual Remark Flashpro II is a product of Naito Densei Machida Seisakusho Co Ltd Flashpro II V850 SA1 Measures when connected Signal Name I o Pin Function Pin Name CSI UART VPP Output Writing voltage VPP VDD I O VDD voltage generation voltage monitoring VDD GND Ground VSS CLK Output Clock output to V850 SA1 X1 Note RESET Output Reset signal RESET SI RxD Input Receive signal SO0 TxD0 SO TxD...

Page 362: ...t pin handling is required when the external device does not acknowledge the output high impedance status 16 5 1 VPP pin In the normal operation mode 0 V is input to VPP pin In the flash memory programming mode 7 8 V writing voltage is supplied to VPP pin The following shows an example of the connection of VPP pin VPP Dedicated flash writer connection pin Pull down resistor RVPP V850 SA1 16 5 2 Se...

Page 363: ... writer connection pin 2 Malfunction of the other device When connecting a dedicated flash writer output or input to a serial interface pin input or output connected to another device input the signal output to the other device may cause the device to malfunction To avoid this isolate the connection to the other device or make the setting so that the input signal to the other device is ignored V85...

Page 364: ...nflict of signals In the flash memory programming mode the signal the reset signal generation circuit outputs conflicts with the signal the dedicated flash writer outputs Therefore isolate the signals on the reset signal generation circuit side Dedicated flash writer connection pin 16 5 4 Port pin When the flash memory programming mode is set all the port pins except the pins which communicate wit...

Page 365: ...ches to flash memory programming mode Selects communication system Manipulates flash memory Ends No Yes Ends Starts 16 6 2 Flash memory programming mode When rewriting the contents of a flash memory using the dedicated flash writer set the V850 SA1 in the flash memory programming mode When switching to modes set VPP pin before releasing reset When performing on board writing change modes using a j...

Page 366: ...on systems Table 16 1 List of Communication Systems VPP Pulse Communication System Remarks 0 CSI0 V850 SA1 performs slave operation MSB first 8 UART0 Communication rate 9600 bps at reset LSB first Others RFU Setting prohibited Caution When UART is selected the receive clock is calculated based on the reset command sent from the dedicated flash writer after receiving VPP pulse 16 6 4 Communication ...

Page 367: ...stem setting and control Status read out command Acquires the status of operations Oscillating frequency setting command Sets the oscillating frequency Erasing timesetting command Sets the erasing time of one shot erase Writing time setting command Sets the writing time of data write Write back time setting command Sets the write back time Baud rate setting command Sets the baud rate when using UA...

Page 368: ...368 MEMO ...

Page 369: ...ister 1 BRG 286 CR00 Capture Compare register 00 RPU 148 CR01 Capture Compare register 01 RPU 149 CR10 Capture Compare register 10 RPU 148 CR11 Capture Compare register 11 RPU 149 CR20 8 bit compare register 2 RPU 180 CR23 16 bit compare register 23 When connected to TM2 TM3 cascade RPU 192 CR30 8 bit compare register 3 RPU 180 CR40 8 bit compare register 4 RPU 180 CR45 16 bit compare register 45 ...

Page 370: ...ter 1 DMAC 318 DRA2 DMA on chip RAM address register 2 DMAC 318 DWC Data wait control register BCU 87 ECR Interrupt source register CPU 56 EGN0 Falling edge specification register INTC 109 332 EGP0 Rising edge specification register INTC 109 332 EIPC Status saving register during interrupt CPU 56 EIPSW Status saving register during interrupt CPU 56 FEPC Status saving registers for NMI CPU 56 FEPSW...

Page 371: ...rrupt control register INTC 117 PIC6 Interrupt control register INTC 117 PM0 Port 0 mode register Port 331 PM1 Port 1 mode register Port 334 PM2 Port 2 mode register Port 337 PM3 Port 3 mode register Port 340 PM4 Port 4 mode register Port 343 PM5 Port 5 mode register Port 343 PM6 Port 6 mode register Port 344 PM9 Port 9 mode register Port 347 PM10 Port 10 mode register Port 349 PM11 Port 11 mode r...

Page 372: ... register INTC 117 SIO0 Serial I O shift register 0 CSI 210 SIO1 Serial I O shift register 1 CSI 210 SIO2 Serial I O shift register 2 CSI 210 SRIC1 Interrupt control register INTC 117 STIC0 Interrupt control register INTC 117 STIC1 Interrupt control register INTC 117 SVA0 Slave address register I2 C 231 SYC System control register CG 84 SYS System status register CG 82 TCL2 Timer clock selection r...

Page 373: ...t control register INTC 150 TMIC2 Interrupt control register INTC 150 TMIC3 Interrupt control register INTC 150 TMIC4 Interrupt control register INTC 150 TMIC5 Interrupt control register INTC 150 TOC0 16 bit timer output control register 0 RPU 154 TOC1 16 bit timer output control register 1 RPU 154 TXS0 Transmit shift register 0 UART 281 TXS1 Transmit shift register 1 UART 281 WDCS Watchdog timer ...

Page 374: ...374 MEMO ...

Page 375: ...ifies reg2 d 1 bit data of displacement i 1 bit data of immediate cccc 4 bit data that indicates condition code bbb 3 bit data specified by bit number 3 Symbol used for operation description 1 2 Symbol Description Assignment GR General register SR System register zero extend n Zero extends n to word length sign extend n Sign extends n to word length load memory a b Reads data of size b from addres...

Page 376: ...hift logically shift right by Logical right shift arithmetically shift right by Arithmetic right shift 4 Symbol used for execution clock description Symbol Description i issue To execute another instruction immediately after instruction execution r repeat To execute same instruction immediately after the instruction l latency To reference result of instruction execution by the next instruction 5 S...

Page 377: ...0 Z 1 Zero Equal NZ NE 1010 Z 0 Not zero Not equal NH 0011 CY or Z 1 Not higher Less than or equal H 1011 CY or Z 0 Higher Greater than N 0100 S 1 Negative P 1100 S 0 Positive T 0101 Always unconditional SA 1101 SAT 1 Saturated LT 1101 S xor OV 1 Less than signed GE 1110 S xor OV 0 Greater than or equal signed LE 0111 S xor OV or Z 1 Less than or equal signed GT 1111 S xor OV or Z 0 Greater than s...

Page 378: ...RRR result GR reg2 GR reg1 1 1 1 imm5 reg2 rrrrr010011iiiii result GR reg2 sign extend imm5 1 1 1 DI 0000011111100000 0000000101100000 PSW ID 1 Maskable interrupt disabled 1 1 1 DIVH reg1 reg2 rrrrr000010RRRRR GR reg2 GR reg2 GR reg2 Note 2 signed division 36 36 36 EI 1000011111100000 0000000101100000 PSW ID 0 Maskable interrupt enabled 1 1 1 HALT 0000011111100000 0000000100100000 Stops 1 1 1 JARL...

Page 379: ...reg1 reg2 rrrrr110111RRRRR iiiiiiiiiiiiiiii GR reg2 GR reg1 Note 3 imm16 Signed multiplication 1 1 2 NOP 0000000000000000 Uses 1 clock cycle without doing anything 1 1 1 NOT reg1 reg2 rrrrr000001RRRRR GR reg2 NOT GR reg1 1 1 1 0 NOT1 bit 3 disp16 reg1 01bbb111110RRRRR dddddddddddddddd adr GR reg1 sign extend disp16 Z flag Not Load memory bit adr bit 3 Store memory bit adr bit 3 Z flag 4 4 4 OR reg...

Page 380: ...re satisfied then GR reg2 00000001H eise GR reg2 00000000H 1 1 1 SET1 bit 3 disp16 reg1 00bbb111110RRRRR dddddddddddddddd adr GR reg1 sign extend disp16 Z flag Not Load memory bit adr bit 3 Store memory bit adr bit 3 1 4 4 4 SHL reg1 reg2 rrrrr111111RRRRR 0000000011000000 GR reg2 GR reg2 logically shift left by GR reg1 1 1 1 0 imm5 reg2 rrrrr010110iiiii GR reg2 GR reg2 logically shift left by zero...

Page 381: ...ddddddddddddddd1 Note 3 adr GR reg1 sign extend disp16 Store memory adr GR reg2 Word 1 1 1 STSR regID reg2 rrrrr111111RRRRR 0000000001000000 GR reg2 SR regID 1 1 1 SUB reg1 reg2 rrrrr001101RRRRR GR reg2 GR reg2 GR reg1 1 1 1 SUBR reg1 reg2 rrrrr001100RRRRR GR reg2 GR reg2 GR reg1 1 1 1 TRAP vector 00000111111iiiii 0000000100000000 EIPC Restored PC EIPSW PSW ECR EICC Interrupt code PSW EP 1 PSW ID ...

Page 382: ...382 MEMO ...

Page 383: ...BCU 27 Bus cycle control register 89 Bus Hold Function 90 Bus Priority 99 Bus Timing 92 Bus width 85 Byte access 85 C Capture compare control register 0 1 153 Capture compare register n0 148 Capture compare register n1 149 Cascade connection 16 bit timer mode 192 CLOCK GENERATION FUNCTION 131 Clock generator CG 27 Clock Output Function 132 Clock selector 220 Command register 82 Communication comma...

Page 384: ...ption table 63 Interval timer 146 158 196 199 207 interval timer 8 bit operation 185 Interval timer mode 202 M Main system clock oscillator 131 Maskable Interrupts 110 Memory address output mode register 71 Memory Block Function 86 Memory Boundary Operation Condition 99 Memory expansion mode register 69 Memory map 62 Multiple interrupt 127 N Non Maskable Interrupt 104 Number of access clocks 84 O ...

Page 385: ...31 Pull up resistance option register 1 335 Pull up resistance option register 10 350 Pull up resistance option register 11 352 Pull up resistance option register 2 338 Pulse width measurement 146 R RAM 27 REAL TIME OUTPUT FUNCTION 327 Real time output buffer registers 322 Real time output port control register 325 Real time output port mode register 324 Recommended use of address space 72 RESET F...

Page 386: ...80 UART1 280 W Wait signal 238 Wake up control circuit 220 Wake up function 265 WATCH TIMER 195 Watch timer 196 198 Watch timer mode control register 197 WATCHDOG TIMER 201 watchdog timer 206 Watchdog timer clock selection register 204 Watchdog timer mode 202 Watchdog timer mode register 120 205 WDCS 204 WDTM 205 Wrap around of CPU address space 61 Writing by Flash Writer 359 ...

Page 387: ...x 02 719 5951 Address North America NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Technical Documentation Dept Fax 49 211 6503 274 South America NEC do Brasil S A Fax 55 11 6465 6829 Asian Nations except Philippines NEC Electronics Singapore Pte Ltd Fax 65 250 3583 Japan NEC Semiconductor Technical Hotline Fax 044 548 7900 I ...

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Summary of Contents for V850/SA1 mPD703015

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NEC V850/SA1 mPD703015, Preliminary User'S Manual

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Summary of Contents for V850/SA1 mPD703015

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